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dual 12-/14-/16-bit, 1 gsps, digital-to-analog converters ad9776/ad9778/ad9779 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005C2007 analog devices, inc. all rights reserved. features low power: 1.0 w @ 1 gsps, 600 mw @ 500 msps, full operating conditions sfdr = 78 dbc to f out = 100 mhz single carrier wcdma aclr = 79 dbc @ 80 mhz if analog output: adjustable 8.7 ma to 31.7 ma, r l = 25 to 50 novel 2, 4, and 8 interpolator/coarse complex modulator allows carrier placement anywhere in dac bandwidth auxiliary dacs allow control of external vga and offset control multiple chip synchronization interface high performance, low noise pll clock multiplier digital inverse sinc filter 100-lead, exposed paddle tqfp package applications wireless infrastructure wcdma, cdma2000, td-scdma, wimax, gsm digital high or low if synthesis internal digital upconversion capability transmit diversity wideband communications: lmds/mmds, point-to-point general description the ad9776/ad9778/ad9779 are dual, 12-/14-/16-bit, high dynamic range, digital-to-analog converters (dacs) that pro- vide a sample rate of 1 gsps, permitting multicarrier generation up to the nyquist frequency. they include features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. the dac outputs are optimized to interface seamlessly with analog quad- rature modulators such as the ad8349. a serial peripheral interface (spi?) provides for programming/readback of many internal parameters. full-scale output curr ent can be programmed over a range of 10 ma to 30 ma. the devices are manufactured on an advanced 0.18 m cmos process and operate on 1.8 v and 3.3 v supplies for a total power consumption of 1.0 w. they are enclosed in 100-lead tqfp packages. product highlights 1. ultralow noise and intermodulation distortion (imd) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies. 2. a proprietary dac output switching technique enhances dynamic performance. 3. the current outputs are easily configured for various single-ended or differential circuit topologies. 4. cmos data input interface with adjustable set up and hold. 5. novel 2 , 4 , and 8 interpolator/coarse complex modulator allows carrier placement anywhere in dac bandwidth. typical signal chain 05361-114 fpga/asic/dsp dc complex i and q dc lo quadrature modulator/ mixer/ amplifier i dac q dac digital interpolation filters ad9779 post dac analog filter a figure 1.
ad9776/ad9778/ad9779 rev. a | page 2 of 56 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 product highlights ........................................................................... 1 typical signal chain ......................................................................... 1 revision history ............................................................................... 2 functional block diagram .............................................................. 3 specifications ..................................................................................... 4 dc specifications ......................................................................... 4 digital specifications ................................................................... 6 digital input data timing specifications ................................. 7 ac specifications .......................................................................... 7 absolute maximum ratings ............................................................ 8 thermal resistance ...................................................................... 8 esd caution .................................................................................. 8 pin configurations and function descriptions ........................... 9 typical performance characteristics ........................................... 15 ter mi nolo g y .................................................................................... 24 theory of operation ...................................................................... 25 serial peripheral interface ......................................................... 25 msb/lsb transfers ..................................................................... 26 spi register map ............................................................................ 27 interpolation filter architecture .................................................. 31 interpolation filter minimum and maximum bandwidth specifications .............................................................................. 35 driving the refclk input ....................................................... 35 internal pll clock multiplier/clock distribution ................ 36 full-scale current generation ................................................. 38 power dissipation ....................................................................... 39 power-down and sleep modes ................................................. 41 interleaved data mode .............................................................. 41 timing information ................................................................... 41 synchronization of input data to dataclk output (pin 37) ........................................................................... 43 synchronization of input data to the refclk input (pin 5 and pin 6) with pll enabled or disabled ............................... 43 evaluation board operation ......................................................... 46 modifying the evaluation board to use the ad8349 on- board quadrature modulator ................................................... 48 evaluation board schematics ................................................... 49 outline dimensions ....................................................................... 56 ordering guide .......................................................................... 56 revision history 3/07rev. 0 to rev. a changes to features.......................................................................... 1 changes to applications .................................................................. 1 changes to general product highlights........................................ 1 added figure 1, renumbered figures sequentially..................... 1 changes to table 1............................................................................ 4 changes to table 2............................................................................ 5 changes to table 3............................................................................ 5 changes to figure 53 and figure 54............................................. 26 changes to table 12........................................................................ 29 changes to power dissipation section ........................................ 39 added table 19, renumbered tables sequentially .................... 41 changes to figure 92 and figure 93............................................. 42 changes to figure 94...................................................................... 42 added new figure 95, renumbered figures sequentially ....... 42 changes to synchronization of input data to the refclk input (pin 5 and pin 6) with pll enabled or disabled section ......... 43 added new figure 96, renumbered figures sequentially ....... 43 changes to figure 106 ................................................................... 51 7/05revision 0: initial version
ad9776/ad9778/ad9779 rev. a | page 3 of 56 functional block diagram 10 10 10 10 clock generation/distribution data assembler digital controller 2 2 sync 1 clock multiplier 2/4/8 16-bit idac clk+ clk? iout1_p iout1_n aux1_p aux1_n aux2_p aux2_n iout2_p iout2_n gain gain gain gain 16-bit qdac 2 sync 1 i latch delay line q latch p2d(15:0) p1d(15:0) sync_o sync_i dataclk_out 2 2 2 n f dac /8 n = 0, 1, 2 ... 7 power-on reset sdo sdio scl k csb serial peripheral interface complex modulator reference and bias vref i120 delay line 0 5361-001 figure 2. functional block diagram
ad9776/ad9778/ad9779 rev. a | page 4 of 56 specifications dc specifications t min to t max , avdd33 = 3.3 v, dvdd33 = 3.3 v, dvdd18 = 1.8 v, cvdd18 =1.8 v, = 20 ma, maximum sample rate, unless otherwise noted. s outf i table 1. ad9776, ad9778, and ad9779 dc specifications ad9776 ad9778 ad9779 parameter min typ max min typ max min typ max unit resolution 12 14 16 bits accuracy differential nonlinearity (dnl) 0.1 0.65 2.1 lsb integral nonlinearity (inl) 0.6 1 3.7 lsb main dac outputs offset error ?0.001 0 +0.001 ?0.001 0 +0.001 ?0.001 0 +0.001 % fsr gain error (with internal reference) 2 2 2 % fsr full-scale output current 1 8.66 20.2 31.66 8.66 20.2 31.66 8.66 20.2 31.66 ma output compliance range ?1.0 +1.0 ?1.0 +1.0 ?1.0 +1.0 v output resistance 10 10 10 m gain dac monotonicity guarant eed guaranteed guaranteed main dac temperature drift offset 0.04 0.04 0.04 ppm/c gain 100 100 100 ppm/c reference voltage 30 30 30 ppm/c aux dac outputs resolution 10 10 10 bits full-scale output current 1 ?1.998 +1.998 ?1.998 +1.998 ?1.998 +1.998 ma output compliance range (source) 0 1.6 0 1.6 0 1.6 v output compliance range (sink) 0.8 1.6 0.8 1.6 0.8 1.6 v output resistance 1 1 1 m aux dac monotonicity guaranteed reference internal reference voltage 1.2 1.2 1.2 v output resistance 5 5 5 k analog supply voltages avdd33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 v cvdd18 1.70 1.8 1.90 1.70 1.8 1.90 1.70 1.8 1.90 v digital supply voltages dvdd33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 v dvdd18 1.70 1.8 1.90 1.70 1.8 1.90 1.70 1.8 1.90 v power consumption 1 mode, f dac = 100 msps, if = 1 mhz 250 300 250 300 250 300 mw 2 mode, f dac = 320 msps, if = 16 mhz, pll off 498 498 498 mw 2 mode, f dac = 320 msps, if = 16 mhz, pll on 588 588 588 mw 4 mode, f dac /4 modulation, f dac = 500 msps, if = 137.5 mhz, q dac off 572 572 572 mw
ad9776/ad9778/ad9779 rev. a | page 5 of 56 ad9776 ad9778 ad9779 parameter min typ max min typ max min typ max unit 8 mode, f dac /4 modulation, f dac = 1 gsps, if = 262.5 mhz 980 980 980 mw power-down mode 2 3.7 2 3.7 2 3.7 mw power supply rejection ratio, avdd33 ?0.3 +0.3 ?0.3 +0.3 ?0.3 +0.3 % fsr/v operating range ?40 +25 +85 ?40 +25 +85 ?40 +25 +85 c 1 based on a 10 k external resistor.
ad9776/ad9778/ad9779 rev. a | page 6 of 56 digital specifications t min to t max , avdd33 = 3.3 v, dvdd33 = 3.3 v, dvdd18 = 1.8 v, cvdd18 = 1.8 v, = 20 ma, maximum sample rate, unless otherwise noted. lvds driver and receiver are compliant to the ieee-1596 reduced range link, unless otherwise noted. s outf i table 2. ad9776, ad9778, and ad9779 digital specifications parameter conditions min typ max unit cmos input logic level input v in logic high 2.0 v input v in logic low 0.8 v maximum input data rate at interpolation 1 300 msps 2 250 msps 4 200 msps 8 125 msps cmos output logic level (dataclk, pin 37) 1 output v out logic high 2.4 v output v out logic low 0.4 v lvds receiver inputs (sync_i+, sync_i?) sync_i+ = v ia , sync_i? = v ib input voltage range, v ia or v ib 825 1575 mv input differential threshold, v idth ?100 +100 mv input differential hysteresis, v idthh ? v idthl 20 mv receiver differential input impedance, r in 2 80 120 lvds input rate 125 msps set-up time, sync_i to dac clock ?0.2 ns hold time, sync_i to dac clock 1 ns lvds driver outputs (sync_o+, sync_o?) sync_o+ = v oa , sync_o? = v ob , 100 termination output voltage high, v oa or v ob 825 1575 mv output voltage low, v oa or v ob 1025 mv output differential voltage, |v od | 150 200 250 mv output offset voltage, v os 1150 1250 mv output impedance, r o single-ended 80 100 120 maximum clock rate 1 ghz dac clock input (clk+, clk?) differential peak-to-peak voltage (clk+, clk?) 3 400 800 2000 mv common-mode voltage 300 400 500 mv maximum clock rate 4 1 gsps serial peripheral interface maximum clock rate (sclk) 40 mhz minimum pulse width high 12.5 ns minimum pulse width low 12.5 ns 1 specification is at a dataclk frequency of 100 mhz into a 1 k load; maximum drive capa bility of 8 ma. at higher speeds or gre ater loads, best practice suggests using an external buffer for this signal. 2 guaranteed at 25c. can drift above 120 at temperatures above 25c. 3 when using the pll, a differential swing of 2 v p-p is recommended. 4 typical maximum clock rate when dvdd18 = cvdd18 = 1.9 v.
ad9776/ad9778/ad9779 rev. a | page 7 of 56 digital input data timing specifications table 3. ad9776, ad9778, and ad9779 digi tal input data timing specifications parameter min typ max unit input data (all modes, ?40c to +85c) 1 set-up time, input data to dataclk +2.5 ns hold time, input data to dataclk ?0.4 ns set-up time, input data to refclk ?0.8 ns hold time, input data to refclk +2.9 ns 1 timing vs. temperature and da ta valid keep out windows ar e delineated in table 19. ac specifications t min to t max , avdd33 = 3.3 v, dvdd33 = 3.3 v, dvdd18 = 1.8 v, cvdd18 = 1.8 v, = 20 ma, maximum sample rate, unless otherwise noted. s outf i table 4. ad9776, ad9778, and ad9779 ac specifications ad9776 ad9778 ad9779 parameter min typ max min typ max min typ max unit spurious free dynamic range (sfdr) f dac = 100 msps, f out = 20 mhz 82 82 82 dbc f dac = 200 msps, f out = 50 mhz 81 81 82 dbc f dac = 400 msps, f out = 70 mhz 80 80 80 dbc f dac = 800 msps, f out = 70 mhz 85 85 87 dbc two-tone intermodulation distortion (imd) f dac = 200 msps, f out = 50 mhz 87 87 91 dbc f dac = 400 msps, f out = 60 mhz 80 85 85 dbc f dac = 400 msps, f out = 80 mhz 75 81 81 dbc f dac = 800 msps, f out = 100 mhz 75 80 81 dbc noise spectral density (nsd) eight-tone, 500 khz tone spacing f dac = 200 msps, f out = 80 mhz ?152 ?155 ?158 dbm/hz f dac = 400 msps, f out = 80 mhz ?155 ?159 ?160 dbm/hz f dac = 800 msps, f out = 80 mhz ?157.5 ?160 ?161 dbm/hz wcdma adjacent channel leakage ratio (aclr), single carrier f dac = 491.52 msps, f out = 100 mhz 76 78 79 dbc f dac = 491.52 msps, f out = 200 mhz 69 73 74 dbc wcdma second adjacent channel leakage ratio (aclr), single carrier f dac = 491.52 msps, f out = 100 mhz 77.5 80 81 dbc f dac = 491.52 msps, f out = 200 mhz 76 78 78 dbc
ad9776/ad9778/ad9779 rev. a | page 8 of 56 absolute maximum ratings table 5. parameter with respect to rating avdd33, dvdd33 agnd, dgnd, cgnd ?0.3 v to +3.6 v dvdd18, cvdd18 agnd, dgnd, cgnd ?0.3 v to +1.98 v agnd dgnd, cgnd ?0.3 v to +0.3 v dgnd agnd, cgnd ?0.3 v to +0.3 v cgnd agnd, dgnd ?0.3 v to +0.3 v i120, vref, iptat agnd ?0.3 v to avdd33 + 0.3 v i out1-p , i out1-n , i out2-p , i out2-n , aux 1-p , aux 1-n , aux 2-p , aux 2-n agnd ?1.0 v to avdd33 + 0.3 v p1d15 to p1d0, p2d15 to p2d0 dgnd ?0.3 v to dvdd33 + 0.3 v dataclk, txenable dgnd ?0.3 v to dvdd33 + 0.3 v clk+, clk? cgnd ?0.3 v to cvdd18 + 0.3 v reset, irq, pll_lock, sync_o+, sync_o?, sync_i+, sync_i?, csb, sclk, sdio, sdo dgnd ?0.3 v to dvdd33 + 0.3 v junction temperature +125c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance 100-lead, thermally enhanced tqfp_ep package, ja = 19.1c/w with the bottom epad soldered to the pcb. with the bottom epad not soldered to the pcb, ja = 27.4c/w. these specifications are valid with no airflow movement. esd caution
ad9776/ad9778/ad9779 rev. a | page 9 of 56 pin configurations and function descriptions 74 vref 73 iptat 72 agnd 69 csb 70 reset 71 irq 75 i120 68 sclk 67 sdio 66 sdo 64 dgnd 63 sync_o+ 62 sync_o? 61 dvdd33 60 dvdd18 59 nc 58 nc 57 nc 56 nc 55 p2d<0> 54 dgnd 53 dvdd18 52 p2d<1> 51 p2d<2> 65 pll_lock pin 1 100 avdd33 99 agnd 98 avdd33 97 agnd 96 avdd33 95 agnd 94 agnd 93 out1_p 92 out1_n 91 agnd 90 aux1_p 89 aux1_n 88 agnd 87 aux2_n 86 aux2_p 85 agnd 84 out2_n 83 out2_p 82 agnd 81 agnd 80 avdd33 79 agnd 78 avdd33 77 agnd 76 avdd33 26 p1d<4> 27 p1d<3> 28 p1d<2> 29 p1d<1> 30 p1d<0> 31 nc 32 dgnd 33 dvdd18 34 nc 35 nc 36 nc 37 dataclk 38 dvdd33 39 txenable 40 p2d<11> 41 p2d<10> 42 p2d<9> 43 dvdd18 44 dgnd 45 p2d<8> 46 p2d<7> 47 p2d<6> 48 p2d<5> 49 p2d<4> 50 p2d<3> 2 cvdd18 3 cgnd 4 cgnd 7 cgnd 6 clk? 5 clk+ 1 cvdd18 8 cgnd 9 cvdd18 10 cvdd18 12 agnd 13 sync_i+ 14 sync_i? 15 dgnd 16 dvdd18 17 p1d<11> 18 p1d<10> 19 p1d<9> 20 p1d<8> 21 p1d<7> 22 dgnd 23 dvdd18 24 p1d<6> 25 p1d<5> 11 cgnd ad9776 top view (not to scale) analog domain digital domain nc = no connect 05361-002 figure 3. ad9776 pin configuration table 6. ad9776 pin function descriptions pin no. mnemonic description 1 cvdd18 1.8 v clock supply. 2 cvdd18 1.8 v clock supply. 3 cgnd clock common. 4 cgnd clock common. 5 clk+ 1 differential clock input. 6 clk? 1 differential clock input. 7 cgnd clock common. 8 cgnd clock common. 9 cvdd18 1.8 v clock supply. 10 cvdd18 1.8 v clock supply. 11 cgnd clock common. 12 agnd analog common. 13 sync_i+ differential synchronization input. 14 sync_i? differential synchronization input. 15 dgnd digital common. 16 dvdd18 1.8 v digital supply. 17 p1d<11> port 1, data input d11 (msb). 18 p1d<10> port 1, data input d10. 19 p1d<9> port 1, data input d9. pin no. mnemonic description 20 p1d<8> port 1, data input d8. 21 p1d<7> port 1, data input d7. 22 dgnd digital common. 23 dvdd18 1.8 v digital supply. 24 p1d<6> port 1, data input d6. 25 p1d<5> port 1, data input d5. 26 p1d<4> port 1, data input d4. 27 p1d<3> port 1, data input d3. 28 p1d<2> port 1, data input d2. 29 p1d<1> port 1, data input d1. 30 p1d<0> port 1, data input d0 (lsb). 31 nc no connect. 32 dgnd digital common. 33 dvdd18 1.8 v digital supply. 34 nc no connect. 35 nc no connect. 36 nc no connect. 37 dataclk data clock output. 38 dvdd33 3.3 v digital supply.
ad9776/ad9778/ad9779 rev. a | page 10 of 56 pin no. mnemonic description 39 txenable transmit enable. 40 p2d<11> port 2, data input d11 (msb). 41 p2d<10> port 2, data input d10. 42 p2d<9> port 2, data input d9. 43 dvdd18 1.8 v digital supply. 44 dgnd digital common. 45 p2d<8> port 2, data input d8. 46 p2d<7> port 2, data input d7. 47 p2d<6> port 2, data input d6. 48 p2d<5> port 2, data input d5. 49 p2d<4> port 2, data input d4. 50 p2d<3> port 2, data input d3. 51 p2d<2> port 2, data input d2. 52 p2d<1> port 2, data input d1. 53 dvdd18 1.8 v digital supply. 54 dgnd digital common. 55 p2d<0> port 2, data input d0 (lsb). 56 nc no connect. 57 nc no connect. 58 nc no connect. 59 nc no connect. 60 dvdd18 1.8 v digital supply. 61 dvdd33 3.3 v digital supply. 62 sync_o? differential synchronization output. 63 sync_o+ differential synchronization output 64 dgnd digital common 65 pll_lock pll lock indicator 66 sdo spi port data output 67 sdio spi port data input/output 68 sclk spi port clock 69 csb spi port chip select bar. 70 reset reset, active high. 71 irq interrupt request. 72 agnd analog common. pin no. mnemonic description 73 iptat factory test pin. output current is proportional to absolute temperature, approximately 10 a at 25c with approximately 20 na/c slope. this pin should remain floating. 74 vref voltage reference output. 75 i120 120 a reference current. 76 avdd33 3.3 v analog supply. 77 agnd analog common. 78 avdd33 3.3 v analog supply. 79 agnd analog common. 80 avdd33 3.3 v analog supply. 81 agnd analog common. 82 agnd analog common. 83 out2_p differential dac current output, channel 2. 84 out2_n differential dac current output, channel 2. 85 agnd analog common. 86 aux2_p auxiliary dac current output, channel 2. 87 aux2_n auxiliary dac current output, channel 2. 88 agnd analog common. 89 aux1_n auxiliary dac current output, channel 1. 90 aux1_p auxiliary dac current output, channel 1. 91 agnd analog common. 92 out1_n differential dac current output, channel 1. 93 out1_p differential dac current output, channel 1. 94 agnd analog common. 95 agnd analog common. 96 avdd33 3.3 v analog supply. 97 agnd analog common. 98 avdd33 3.3 v analog supply. 99 agnd analog common. 100 avdd33 3.3 v analog supply. 1 the combined differential clock input at the clk+ and clkC pins are referred to as refclk.
ad9776/ad9778/ad9779 rev. a | page 11 of 56 74 vref 73 iptat 72 agnd 69 csb 70 reset 71 irq 75 i120 68 sclk 67 sdio 66 sdo 64 dgnd 63 sync_o+ 62 sync_o? 61 dvdd33 60 dvdd18 59 nc 58 nc 57 p2d<0> 56 p2d<1> 55 p2d<2> 54 dgnd 53 dvdd18 52 p2d<3> 51 p2d<4> 65 pll_lock pin 1 100 avdd33 99 agnd 98 avdd33 97 agnd 96 avdd33 95 agnd 94 agnd 93 out1_p 92 out1_n 91 agnd 90 aux1_p 89 aux1_n 88 agnd 87 aux2_n 86 aux2_p 85 agnd 84 out2_n 83 out2_p 82 agnd 81 agnd 80 avdd33 79 agnd 78 avdd33 77 agnd 76 avdd33 26 p1d<6> 27 p1d<5> 28 p1d<4> 29 p1d<3> 30 p1d<2> 31 p1d<1> 32 dgnd 33 dvdd18 34 p1d<0> 35 nc 36 nc 37 dataclk 38 dvdd33 39 txenable 40 p2d<13> 41 p2d<12> 42 p2d<11> 43 dvdd18 44 dgnd 45 p2d<10> 46 p2d<9> 47 p2d<8> 48 p2d<7> 49 p2d<6> 50 p2d<5> 2 cvdd18 3 cgnd 4 cgnd 7 cgnd 6 clk? 5 clk+ 1 cvdd18 8 cgnd 9 cvdd18 10 cvdd18 12 agnd 13 sync_i+ 14 sync_i? 15 dgnd 16 dvdd18 17 p1d<13> 18 p1d<12> 19 p1d<11> 20 p1d<10> 21 p1d<9> 22 dgnd 23 dvdd18 24 p1d<8> 25 p1d<7> 11 cgnd ad9778 top view (not to scale) analog domain digital domain nc = no connect 05361-003 figure 4. ad9778 pin configuration table 7. ad9778 pin function description pin no. mnemonic description 1 cvdd18 1.8 v clock supply. 2 cvdd18 1.8 v clock supply. 3 cgnd clock common. 4 cgnd clock common. 5 clk+ 1 differential clock input. 6 clk? 1 differential clock input. 7 cgnd clock common. 8 cgnd clock common. 9 cvdd18 1.8 v clock supply. 10 cvdd18 1.8 v clock supply. 11 cgnd clock common. 12 agnd analog common. 13 sync_i+ differential synchronization input. 14 sync_i? differential synchronization input. 15 dgnd digital common. 16 dvdd18 1.8 v digital supply. 17 p1d<13> port 1, data input d13 (msb). 18 p1d<12> port 1, data input d12. 19 p1d<11> port 1, data input d11. 20 p1d<10> port 1, data input d10. pin no. mnemonic description 21 p1d<9> port 1, data input d9. 22 dgnd digital common. 23 dvdd18 1.8 v digital supply. 24 p1d<8> port 1, data input d8. 25 p1d<7> port 1, data input d7. 26 p1d<6> port 1, data input d6. 27 p1d<5> port 1, data input d5. 28 p1d<4> port 1, data input d4. 29 p1d<3> port 1, data input d3. 30 p1d<2> port 1, data input d2. 31 p1d<1> port 1, data input d1. 32 dgnd digital common. 33 dvdd18 1.8 v digital supply. 34 p1d<0> port 1, data input d0 (lsb). 35 nc no connect. 36 nc no connect. 37 dataclk data clock output. 38 dvdd33 3.3 v digital supply. 39 txenable transmit enable. 40 p2d<13> port 2, data input d13 (msb).
ad9776/ad9778/ad9779 rev. a | page 12 of 56 pin no. mnemonic description 41 p2d<12> port 2, data input d12. 42 p2d<11> port 2, data input d11. 43 dvdd18 1.8 v digital supply. 44 dgnd digital common. 45 p2d<10> port 2, data input d10. 46 p2d<9> port 2, data input d9. 47 p2d<8> port 2, data input d8. 48 p2d<7> port 2, data input d7. 49 p2d<6> port 2, data input d6. 50 p2d<5> port 2, data input d5. 51 p2d<4> port 2, data input d4. 52 p2d<3> port 2, data input d3. 53 dvdd18 1.8 v digital supply. 54 dgnd digital common. 55 p2d<2> port 2, data input d2. 56 p2d<1> port 2, data input d1. 57 p2d<0> port 2, data input d0 (lsb). 58 nc no connect. 59 nc no connect. 60 dvdd18 1.8 v digital supply. 61 dvdd33 3.3 v digital supply. 62 sync_o? differential synchronization output. 63 sync_o+ differential synchronization output. 64 dgnd digital common. 65 pll_lock pll lock indicator. 66 sdo spi port data output. 67 sdio spi port data input/output. 68 sclk spi port clock. 69 csb spi port chip select bar. 70 reset reset, active high. 71 irq interrupt request. 72 agnd analog common. 73 iptat factory test pin. output current is proportional to absolute temperature, approximately 10 a at 25c with approximately 20 na/c slope. this pin should remain floating. pin no. mnemonic description 74 vref voltage reference output. 75 i120 120 a reference current. 76 avdd33 3.3 v analog supply. 77 agnd analog common. 78 avdd33 3.3 v analog supply. 79 agnd analog common. 80 avdd33 3.3 v analog supply. 81 agnd analog common. 82 agnd analog common. 83 out2_p differential dac current output, channel 2. 84 out2_n differential dac current output, channel 2. 85 agnd analog common. 86 aux2_p auxiliary dac current output, channel 2. 87 aux2_n auxiliary dac current output, channel 2. 88 agnd analog common. 89 aux1_n auxiliary dac current output, channel 1. 90 aux1_p auxiliary dac current output, channel 1. 91 agnd analog common. 92 out1_n differential dac current output, channel 1. 93 out1_p differential dac current output, channel 1. 94 agnd analog common. 95 agnd analog common. 96 avdd33 3.3 v analog supply. 97 agnd analog common. 98 avdd33 3.3 v analog supply. 99 agnd analog common. 100 avdd33 3.3 v analog supply. 1 the combined differential clock input at the clk+ and clkC pins are referred to as refclk.
ad9776/ad9778/ad9779 rev. a | page 13 of 56 74 vref 73 iptat 72 agnd 69 csb 70 reset 71 irq 75 i120 68 sclk 67 sdio 66 sdo 64 dgnd 63 sync_o+ 62 sync_o? 61 dvdd33 60 dvdd18 59 p2d<0> 58 p2d<1> 57 p2d<2> 56 p2d<3> 55 p2d<4> 54 dgnd 53 dvdd18 52 p2d<5> 51 p2d<6> 65 pll_lock pin 1 100 avdd33 99 agnd 98 avdd33 97 agnd 96 avdd33 95 agnd 94 agnd 93 out1_p 92 out1_n 91 agnd 90 aux1_p 89 aux1_n 88 agnd 87 aux2_n 86 aux2_p 85 agnd 84 out2_n 83 out2_p 82 agnd 81 agnd 80 avdd33 79 agnd 78 avdd33 77 agnd 76 avdd33 26 p1d<8> 27 p1d<7> 28 p1d<6> 29 p1d<5> 30 p1d<4> 31 p1d<3> 32 dgnd 33 dvdd18 34 p1d<2> 35 p1d<1> 36 p1d<0> 37 dataclk 38 dvdd33 39 txenable 40 p2d<15> 41 p2d<14> 42 p2d<13> 43 dvdd18 44 dgnd 45 p2d<12> 46 p2d<11> 47 p2d<10> 48 p2d<9> 49 p2d<8> 50 p2d<7> 2 cvdd18 3 cgnd 4 cgnd 7 cgnd 6 clk? 5 clk+ 1 cvdd18 8 cgnd 9 cvdd18 10 cvdd18 12 agnd 13 sync_i+ 14 sync_i? 15 dgnd 16 dvdd18 17 p1d<15> 18 p1d<14> 19 p1d<13> 20 p1d<12> 21 p1d<11> 22 dgnd 23 dvdd18 24 p1d<10> 25 p1d<9> 11 cgnd ad9779 top view (not to scale) analog domain digital domain 05361-004 figure 5. ad9779 pin configuration table 8. ad9779 pin function descriptions pin no. mnemonic description 1 cvdd18 1.8 v clock supply. 2 cvdd18 1.8 v clock supply. 3 cgnd clock common. 4 cgnd clock common. 5 clk+ 1 differential clock input. 6 clk? 1 differential clock input. 7 cgnd clock common. 8 cgnd clock common. 9 cvdd18 1.8 v clock supply. 10 cvdd18 1.8 v clock supply. 11 cgnd clock common. 12 agnd analog common. 13 sync_i+ differential synchronization input. 14 sync_i? differential synchronization input. 15 dgnd digital common. 16 dvdd18 1.8 v digital supply. 17 p1d<15> port 1, data input d15 (msb). 18 p1d<14> port 1, data input d14. 19 p1d<13> port 1, data input d13. 20 p1d<12> port 1, data input d12. 21 p1d<11> port 1, data input d11. pin no. mnemonic description 22 dgnd digital common. 23 dvdd18 1.8 v digital supply. 24 p1d<10> port 1, data input d10. 25 p1d<9> port 1, data input d9. 26 p1d<8> port 1, data input d8. 27 p1d<7> port 1, data input d7. 28 p1d<6> port 1, data input d6. 29 p1d<5> port 1, data input d5. 30 p1d<4> port 1, data input d4. 31 p1d<3> port 1, data input d3. 32 dgnd digital common. 33 dvdd18 1.8 v digital supply. 34 p1d<2> port 1, data input d2. 35 p1d<1> port 1, data input d1. 36 p1d<0> port 1, data input d0 (lsb). 37 dataclk data clock output. 38 dvdd33 3.3 v digital supply. 39 txenable transmit enable. 40 p2d<15> port 2, data input d15 (msb). 41 p2d<14> port 2, data input d14. 42 p2d<13> port 2, data input d13.
ad9776/ad9778/ad9779 rev. a | page 14 of 56 pin no. mnemonic description 43 dvdd18 1.8 v digital supply. 44 dgnd digital common. 45 p2d<12> port 2, data input d12. 46 p2d<11> port 2, data input d11. 47 p2d<10> port 2, data input d10. 48 p2d<9> port 2, data input d9. 49 p2d<8> port 2, data input d8. 50 p2d<7> port 2, data input d7. 51 p2d<6> port 2, data input d6. 52 p2d<5> port 2, data input d5. 53 dvdd18 1.8 v digital supply. 54 dgnd digital common. 55 p2d<4> port 2, data input d4. 56 p2d<3> port 2, data input d3. 57 p2d<2> port 2, data input d2. 58 p2d<1> port 2, data input d1. 59 p2d<0> port 2, data input d0 (lsb). 60 dvdd18 1.8 v digital supply. 61 dvdd33 3.3 v digital supply. 62 sync_o? differential synchronization output. 63 sync_o+ differential synchronization output. 64 dgnd digital common. 65 pll_lock pll lock indicator. 66 spi_sdo spi port data output. 67 spi_sdio spi port data input/output. 68 sclk spi port clock. 69 spi_csb spi port chip select bar. 70 reset reset, active high. 71 irq interrupt request. 72 agnd analog common. 73 iptat factory test pin. output current is proportional to absolute temperature, approximately 10 a at 25c with approximately 20 na/c slope. this pin should remain floating. pin no. mnemonic description 74 vref voltage reference output. 75 i120 120 a reference current. 76 avdd33 3.3 v analog supply. 77 agnd analog common. 78 avdd33 3.3 v analog supply. 79 agnd analog common. 80 avdd33 3.3 v analog supply. 81 agnd analog common. 82 agnd analog common. 83 out2_p differential dac current output, channel 2. 84 out2_n differential dac current output, channel 2. 85 agnd analog common. 86 aux2_p auxiliary dac current output, channel 2. 87 aux2_n auxiliary dac current output, channel 2. 88 agnd analog common. 89 aux1_n auxiliary dac current output, channel 1. 90 aux1_p auxiliary dac current output, channel 1. 91 agnd analog common. 92 out1_n differential dac current output, channel 1. 93 out1_p differential dac current output, channel 1. 94 agnd analog common. 95 agnd analog common. 96 avdd33 3.3 v analog supply. 97 agnd analog common. 98 avdd33 3.3 v analog supply. 99 agnd analog common. 100 avdd33 3.3 v analog supply. 1 the combined differential clock input at the clk+ and clkC pins are referred to as refclk.
ad9776/ad9778/ad9779 rev. a | page 15 of 56 typical performance characteristics 4 ?6 0 code inl (16-bit lsb) 3 2 1 0 ?1 ?2 ?3 ?4 ?5 10k 20k 30k 60k 50k 40k 05361-005 figure 6. ad9779 typical inl 1.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 0 60k 50k 40k 30k 20k 10k code dnl (16-bit lsb) 05361-006 figure 7. ad9779 typical dnl 100 50 0 100 f out (mhz) sfdr (dbc) 90 80 70 60 20 40 60 80 f data = 160msps f data = 200msps f data = 250msps 05361-007 figure 8. ad9779 in-band sfdr vs. f out , 1x interpolation 100 50 0 100 f out (mhz) sfdr (dbc) 90 80 70 60 20 40 60 80 f data = 160msps f data = 200msps f data = 250msps 05361-008 figure 9. ad9779 in-band sfdr vs. f out , 2 interpolation 100 50 0 100 f out (mhz) sfdr (dbc) 90 80 70 60 20 40 60 80 f data = 100msps f data = 200msps f data = 150msps 05361-009 figure 10. ad9779 in-band sfdr vs. f out , 4 interpolation 100 50 0 50 f out (mhz) sfdr (dbc) 90 80 70 60 10 20 30 40 f data = 50msps f data = 100msps f data = 125msps 05361-010 figure 11. ad9779 in-band sfdr vs. f out , 8 interpolation
ad9776/ad9778/ad9779 rev. a | page 16 of 56 100 50 0 100 f out (mhz) sfdr (dbc) 90 80 70 60 20 40 60 80 f data = 200msps f data = 160msps f data = 250msps 05361-011 figure 12. ad9779 out-of-band sfdr vs. f out , 2 interpolation 100 50 0 100 f out (mhz) sfdr (dbc) 90 80 70 60 20 40 60 80 f data = 150msps f data = 100msps f data = 200msps 05361-012 figure 13. ad9779 out-of-band sfdr vs. f out , 4 interpolation 100 50 0 50 f out (mhz) sfdr (dbc) 90 80 70 60 10 20 30 40 f data = 50msps f data = 100msps f data = 125msps 05361-013 figure 14. ad9779 out-of-band sfdr vs. f out , 8 interpolation 100 50 04 f out (mhz) sfdr (dbc) 0 90 80 70 60 10 20 30 pll off pll on 05361-014 figure 15. ad9779 in-band sfdr, 4 interpolation, f data = 100 msps, pll on/off 100 50 08 f out (mhz) sfdr (dbc) 0 90 80 70 60 20 40 60 ?3dbfs 0dbfs ?6dbfs 05361-015 figure 16. ad9779 in-band sfdr vs. digital full-scale input 100 50 08 f out (mhz) sfdr (dbc) 0 90 80 70 60 20 40 60 10ma 20ma 30ma 05361-016 figure 17. ad9779 in-band sfdr vs. output full-scale current
ad9776/ad9778/ad9779 rev. a | page 17 of 56 100 50 0 120 f out (mhz) imd (dbc) 90 80 70 60 20 40 60 80 100 f data = 200msps f data = 250msps f data = 160msps 05361-017 figure 18. ad9779 third-order imd vs. f out , 1 interpolation 100 50 0 20 40 60 80 100 120 140 160 180 200 220 f out (mhz) imd (dbc) 90 80 70 60 f data = 160msps f data = 250msps f data = 200msps 05361-018 figure 19. ad9779 third-order imd vs. f out , 2 interpolation 100 50 0 400 f out (mhz) imd (dbc) 90 80 70 60 40 80 120 160 200 240 280 320 360 f data = 150msps f data = 200msps f data = 100msps 05361-019 figure 20. ad9779 third-order imd vs. f out , 4 interpolation f out (mhz) imd (dbc) f data = 75msps f data = 125msps f data = 100msps 90 100 80 70 60 50 450 425 400 375 350 325 300 275 250 225 200 175 150 125 100 75 50 25 0 f data = 50msps 05361-020 figure 21. ad9779 third-order imd vs. f out , 8 interpolation 100 50 0 200 f out (mhz) imd (dbc) 90 80 70 60 100 20 40 60 80 120 140 160 180 pll off pll on 05361-021 figure 22. ad9779 third-order imd vs. f out , 4 interpolation, f data = 100 msps, pll on vs. pll off 100 95 50 55 0 400360 f out (mhz) imd (dbc) 90 80 85 70 75 60 65 40 80 120 160 200 240 280 320 05361-022 figure 23. ad9779 third-order imd vs. f out , over 50 parts,4 interpolation, f data = 200 msps
ad9776/ad9778/ad9779 rev. a | page 18 of 56 100 50 55 60 65 70 75 80 85 90 95 0 400 f out (mhz) imd (dbc) 80 160 240 360320 40 120 200 280 05361-117 0dbfs ?3dbfs ?6dbfs figure 24. imd performance vs. digital full-scale input, 4 interpolation, f data = 200 msps 100 50 55 60 65 70 75 80 85 90 95 0 400 f out (mhz) imd (dbc) 80 160 240 360320 40 120 200 280 05361-118 20ma 10ma 30ma figure 25. imd performance vs. full-scale output current, 4 interpolation, f data = 200 msps stop 400.0mhz sweep 1.203s (601 pts) vbw 20khz start 1.0mhz *res bw 20khz ref 0dbm *peak log 10db/ lgav 51 w1 s3 (f): ftun swp s2 fc aa *atten 20db ext ref dc coupled 05361-023 figure 26. ad9779 single tone, 4 interpolation, f data = 100 msps, f out = 30 mhz stop 400.0mhz sweep 1.203s (601 pts) vbw 20khz start 1.0mhz *res bw 20khz ref 0dbm *peak log 10db/ lgav 51 w1 s3 (f): ftun swp s2 fc aa *atten 20db ext ref dc coupled 05361-024 figure 27. ad9779 two-tone spectrum, 4 interpolation, f data = 100 msps, f out = 30 mhz, 35 mhz ?142 ?146 ?150 ?154 ?158 ?162 ?166 ?170 0 f out (mhz) nsd (dbm/hz) 20 40 60 80 0dbfs ?3dbfs ?6dbfs 05361-025 figure 28. ad9779 noise spectral density vs. digital full-scale of single-tone input, f data = 200 msps, 2 interpolation ?150 ?170 0 100 f out (mhz) nsd (dbm/hz) ?154 ?158 ?162 ?166 20 40 60 80 f dac = 800msps f dac = 400msps f dac = 200msps 05361-026 figure 29. ad9779 noise spectral density vs. f dac , eight-tone input with 500 khz spacing, f data = 200 msps
ad9776/ad9778/ad9779 rev. a | page 19 of 56 ?150 ?170 0 100 f out (mhz) nsd (dbm/hz) ?154 ?158 ?162 ?166 20 40 60 80 f dac = 800msps f dac = 400msps f dac = 200msps 05361-027 figure 30. ad9779 noise spectral density vs. f dac , single-tone input at ?6 dbfs ?55 ?90 0 260 f out (mhz) aclr (dbc) ?60 ?65 ?70 ?75 ?80 ?85 20 40 60 80 100 120 140 160 180 200 220 240 ?6dbfs ?3dbfs 0dbfs ? pll on 0dbfs 05361-028 figure 31. ad9779 aclr for first adjacent band wcdma, 4 interpolation, f data = 122.88 msps, on-chip modulation translates baseband signal to if ?55 ?90 0 260 f out (mhz) aclr (dbc) ?60 ?65 ?70 ?75 ?80 ?85 20 40 60 80 100 120 140 160 180 200 220 240 ?6dbfs ?3dbfs 0dbfs ? pll on 0dbfs 05361-029 figure 32. ad9779 aclr for second adjacent band wcdma, 4 interpolation, f data = 122.88 msps. on-chip modulation translates baseband signal to if ?55 ?90 0 260 f out (mhz) aclr (dbc) ?60 ?65 ?70 ?75 ?80 ?85 20 40 60 80 100 120 140 160 180 200 220 240 ?6dbfs ?3dbfs 0dbfs ? pll on 0dbfs 05361-030 figure 33. ad9779 aclr for third adjacent band wcdma, 4 interpolation, f data = 122.88 msps, on-chip modulation translates baseband signal to if
ad9776/ad9778/ad9779 rev. a | page 20 of 56 span 50mhz sweep 162.2ms (601 pts) vbw 300khz center 143.88mhz *res bw 30khz rms results carrier power ?12.49dbm/ 3.84000mhz freq offset 5.000mhz 10.00mhz 15.00mhz ref bw 3.840mhz 3.840mhz 3.840mhz dbc ?76.75 ?80.94 ?79.95 dbm ?89.23 ?93.43 ?92.44 lower dbc ?77.42 ?80.47 ?78.96 dbm ?89.91 ?92.96 ?91.45 upper ref ?25.28dbm *avg log 10db/ pavg 10 w1 s2 *atten 4db ext ref 05361-031 figure 34. ad9779 wcdma signal, 4 interpolation, f data =122.88 msps, f dac /4 modulation span 50mhz sweep 162.2ms (601 pts) vbw 300khz center 151.38mhz *res bw 30khz 1 ?17.87dbm 2 ?20.65dbm 3 ?18.26dbm 4 ?18.23dbm total carrier power ?12.61dbm/15.3600mhz ref carrier power ?17.87dbm/3.84000mhz freq offset 5.000mhz 10.00mhz 15.00mhz integ bw 3.840mhz 3.840mhz 3.840mhz dbc ?67.70 ?70.00 ?71.65 dbm ?85.57 ?97.87 ?99.52 lower dbc ?67.70 ?69.32 ?71.00 dbm ?85.57 ?87.19 ?88.88 upper ref ?30.28dbm *avg log 10db/ pavg 10 w1 s2 *atten 4db ext ref 05361-032 figure 35. ad9779 multicarrier wcdma signal, 4 interpolation, f dac =122.88 msps, f dac /4 modulation 1.5 0 code inl (14-bit lsb) 10k 1.0 0.5 0 ?0.5 ?1.0 ?1.5 2k 4k 6k 8k 05361-033 figure 36. ad9778 typical inl 0.6 0 code dnl (14-bit lsb) ?0.2 ?1.0 16k 14k 12k 10k 8k 6k 4k 2k 0.4 0.2 0 ?0.4 ?0.6 ?0.8 05361-034 figure 37. ad9778 typical dnl
ad9776/ad9778/ad9779 rev. a | page 21 of 56 100 50 0 400 f out (mhz) imd (dbc) 90 80 70 60 40 80 120 160 200 240 280 320 360 4 200msps 4 150msps 4 100msps 05361-035 figure 38. ad9778 imd, 4 interpolation 100 50 0 100 f out (mhz) sfdr (dbc) 90 80 70 60 20 40 60 80 f data = 250msps f data = 200msps f data = 160msps 05361-036 figure 39. ad9778 in-band sfdr, 2 interpolation ?90 0 250 f out (mhz) aclr (dbc) ?70 ?80 ?60 25 50 75 100 125 150 175 200 225 1st adj chan 2nd adj chan 3rd adj chan 05361-037 figure 40. ad9778 aclr, single-carrier wcdma, 4 interpolation, f data = 122.88 msps, amplitude = ?3 dbfs span 50mhz sweep 162.2ms (601 pts) vbw 300khz center 143.88mhz *res bw 30khz rms results carrier power ?12.74dbm/ 3.84000mhz freq offset 5.000mhz 10.00mhz 15.00mhz ref bw 3.884mhz 3.840mhz 3.840mhz dbc ?76.49 ?80.13 ?80.90 dbm ?89.23 ?92.87 ?93.64 lower dbc ?76.89 ?80.02 ?79.53 dbm ?89.63 ?92.76 ?92.27 upper ref ?25.39dbm *avg log 10db/ pavg 10 w1 s2 *atten 4db 05361-038 figure 41. ad9778 aclr, f data = 122.88 msps, 4 interpolation, f dac /4 modulation ?150 ?170 0 100 f out (mhz) nsd (dbm/hz) ?154 ?158 ?162 ?166 20 40 60 80 f dac = 800msps f dac = 400msps f dac = 200msps 05361-039 figure 42. ad9778 noise spectral density vs. f dac eight-tone input with 500 khz spacing, f data = 200 msps ?150 ?170 0 100 f out (mhz) nsd (dbm/hz) ?154 ?158 ?162 ?166 20 40 60 80 f dac = 800msps f dac = 400msps f dac = 200msps 05361-040 figure 43. ad9778 noise spectral density vs. f dac single-tone input at ?6 dbfs, f data = 200 msps
ad9776/ad9778/ad9779 rev. a | page 22 of 56 0.4 0 4096 code inl (12-bit lsb) ?0.4 512 1024 2560 2048 1536 3072 3584 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 05361-041 figure 44. ad9776 typical inl 0.20 0 4096 code dnl (12-bit lsb) 2048 ?0.20 512 1024 1536 2560 3072 3584 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 05361-042 figure 45. ad9776 typical dnl 100 50 0 400 f out (mhz) imd (dbc) 40 80 120 160 200 240 280 320 360 4 200msps 4 100msps 4 150msps 95 90 85 80 75 70 65 60 55 05361-043 figure 46. ad9776 imd, 4 interpolation 100 50 0 100 f out (mhz) sfdr (dbc) 90 80 70 60 20 40 60 80 f data = 250msps f data = 200msps f data = 160msps 05361-044 figure 47. ad9776 in-band sfdr, 2 interpolation ?90 0 250 f out (mhz) aclr (dbc) ?55 25 50 75 100 125 150 175 200 225 1st adj chan 2nd adj chan 3rd adj chan ?60 ?65 ?70 ?75 ?80 ?85 05361-045 figure 48. ad9776 aclr, f data = 122.88 msps, 4 interpolation, f dac /4 modulation span 50mhz sweep 162.2ms (601 pts) vbw 300khz center 143.88mhz *res bw 30khz rms results carrier power ?12.67dbm/ 3.84000mhz freq offset 5.000mhz 10.00mhz 15.00mhz ref bw 3.884mhz 3.840mhz 3.840mhz dbc ?75.00 ?78.05 ?77.73 dbm ?87.67 ?90.73 ?90.41 lower dbc ?75.30 ?77.99 ?77.50 dbm ?87.97 ?90.66 ?90.17 upper ref ?25.29dbm *avg log 10db/ pavg 10 w1 s2 *atten 4db 05361-046 figure 49. ad9776, single carrier wcdma, 4 interpolation, f data = 122.88 msps, amplitude = ?3 dbfs
ad9776/ad9778/ad9779 rev. a | page 23 of 56 ?150 ?170 0 100 f out (mhz) nsd (dbm/hz) ?154 ?158 ?162 ?166 20 40 60 80 f dac = 800msps f dac = 400msps f dac = 200msps 10 30 50 70 90 05361-047 figure 50. ad9776 noise spectral density vs. f dac , eight-tone input with 500 khz spacing, f data = 200 msps ?150 ?170 0 100 f out (mhz) nsd (dbm/hz) ?154 ?158 ?162 ?166 20 40 60 80 f dac = 800msps f dac = 400msps f dac = 200msps 10 30 50 70 90 05361-048 figure 51. ad9776 noise spectral density vs. f dac , single-tone input at ?6 dbfs, f data = 200 msps
ad9776/ad9778/ad9779 rev. a | page 24 of 56 terminology integral nonlinearity (inl) inl is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. differential nonlinearity (dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. monotonicity a dac is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current from the ideal of zero is called offset error. for i outa , 0 ma output is expected when the inputs are all 0s. for i outb , 0 ma output is expected when all inputs are set to 1. b gain error the difference between the actual and ideal output span. the actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0. output compliance range the range of allowable voltage at the output of a current-output dac. operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. temp er atu re d r i f t temperature drift is specified as the maximum change from the ambient (25c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full-scale range (fsr) per degree celsius. for reference drift, the drift is reported in ppm per degree celsius. power supply rejection (psr) the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. settling time the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. in-band spurious free dynamic range (sfdr) the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal between dc and the frequency equal to half the input data rate. out-of-band spurious free dynamic range (sfdr) the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the band that starts at the frequency of the input data rate and ends at the nyquist frequency of the dac output sample rate. normally, energy in this band is rejected by the interpolation filters. this specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths to the dac output. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured fundamental. it is expressed as a percentage or in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels. interpolation filter if the digital inputs to the dac are sampled at a multiple rate of f data (interpolation rate), a digital filter can be constructed that has a sharp transition band near f data /2. images that typically appear around f dac (output data rate) can be greatly suppressed. adjacent channel leakage ratio (aclr) the ratio in dbc between the measured power within a channel relative to its adjacent channel. complex image rejection in a traditional two-part upconversion, two images are created around the second if frequency. these images have the effect of wasting transmitter power and system bandwidth. by placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second if can be rejected.
ad9776/ad9778/ad9779 rev. a | page 25 of 56 theory of operation the ad9776/ad9778/ad9779 combine many features that make them very attractive dacs for wired and wireless communications systems. the dual digital signal path and dual dac structure allow an easy interface with common quadrature modulators when designing single sideband transmitters. the speed and performance of the parts allow wider bandwidths and more carriers to be synthesized than in previously available dacs. the digital engine uses a break- through filter architecture that combines the interpolation with a digital quadrature modulator. this allows the parts to conduct digital quadrature frequency upconversion. they also have features that allow simplified synchronization with incoming data and between multiple parts. the serial port configuration is controlled by register 0x00, bits<6:7>. it is important to note that the configuration changes immediately upon writing to the last bit of the byte. for multi- byte transfers, writing to this register can occur during the middle of a communication cycle. care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle. the same considerations apply to setting the software reset, reset (register 0x00, bit 5) or pulling the reset pin (pin 70) high. all registers are set to their default values, except register 0x00 and register 0x04, which remain unchanged. use of only single-byte transfers when changing serial port configurations or initiating a software reset is recommended to prevent unexpected device behavior. as described in this section, all serial port data is transferred to/from the device in synchronization to the sclk pin. if synchronization is lost, the device has the ability to asynchro- nously terminate an i/o operation, putting the serial port controller into a known state and, thereby, regaining synchronization. serial peripheral interface spi_sdo spi port 66 spi_sdi 67 spi_sclk 68 spi_csb 69 05361-049 figure 52. spi port the serial port is a flexible, synchronous serial communications port allowing easy interface to many industry-standard micro- controllers and microprocessors. the serial i/o is compatible with most synchronous transfer formats, including both the motorola spi ? and intel ? ssr protocols. the interface allows read/write access to all registers that configure the ad9776/ ad9778/ad9779. single or multiple byte transfers are sup- ported, as well as msb-first or lsb-first transfer formats. the serial interface ports can be configured as a single pin i/o (sdio) or two unidirectional pins for input/output (sdio/sdo). general operation of the serial interface there are two phases to a communication cycle with the ad977x. phase 1 is the instruction cycle (the writing of an instruction byte into the device), coincident with the first eight sclk rising edges. the instruction byte provides the serial port controller with information regarding the data transfer cycle, phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcoming data transfer is a read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. the first eight sclk rising edges of each communication cycle are used to write the instruction byte into the device. a logic high on the csb pin followed by a logic low resets the spi port timing to the initial state of the instruction cycle. from this state, the next eight rising sclk edges represent the instruction bits of the current i/o operation, regardless of the state of the internal registers or the other signal levels at the inputs to the spi port. if the spi port is in an instruction cycle or a data transfer cycle, none of the present data is written. the remaining sclk edges are for phase 2 of the communica- tion cycle. phase 2 is the actual data transfer between the device and the system controller. phase 2 of the communication cycle is a transfer of one, two, three, or four data bytes as determined by the instruction byte. using one multibyte transfer is preferred. single-byte data transfers are useful in reducing cpu overhead when register access requires only one byte. registers change immediately upon writing to the last bit of each transfer byte. instruction byte the instruction byte contains the information shown in table 9 . table 9. spi instruction byte msb lsb i7 i6 i5 i4 i3 i2 i1 i0 r/ w n1 n0 a4 a3 a2 a1 a0 r/ w , bit 7 of the instruction byte, determines whether a read or a write data transfer occurs after the instruction byte write. logic high indicates a read operation. logic 0 indicates a write operation. n1 and n0, bit 6 and bit 5 of the instruction byte, determine the number of bytes to be transferred during the data transfer cycle. the bit decodes are listed in table 10 . a4, a3, a2, a1, and a0bit 4, bit 3, bit 2, bit 1, and bit 0, respec- tively, of the instruction byte determine the register that is accessed during the data transfer portion of the communication cycle.
ad9776/ad9778/ad9779 rev. a | page 26 of 56 for multibyte transfers, this address is the starting byte address. the remaining register addresses are generated by the device based on the lsb-first bit (register 0x00, bit 6). table 10. byte transfer count n1 n0 description 0 0 transfer one byte 0 1 transfer three bytes 1 0 transfer two bytes 1 1 transfer four bytes serial interface port pin descriptions serial clock (sclk) the serial clock pin synchronizes data to and from the device and to run the internal state machines. the maximum frequency of sclk is 40 mhz. all data input is registered on the rising edge of sclk. all data is driven out on the falling edge of sclk. chip select (csb) active low input starts and gates a communication cycle. it allows more than one device to be used on the same serial communications lines. the sdo and sdio pins go to a high impedance state when this input is high. chip select should stay low during the entire communication cycle. serial data i/o (sdio) data is always written into the device on this pin. however, this pin can be used as a bidirectional data line. the configuration of this pin is controlled by register 0x00, bit 7. the default is logic 0, configuring the sdio pin as unidirectional. serial data out (sdo) data is read from this pin for protocols that use separate lines for transmitting and receiving data. in the case where the device operates in a single bidirectional i/o mode, this pin does not output data and is set to a high impedance state. msb/lsb transfers the serial port can support both msb-first and lsb-first data formats. this functionality is controlled by register bit lsb_first (register 0x00, bit 6). the default is msb-first (lsb-first = 0). when lsb-first = 0 (msb-first) the instruction and data bit must be written from msb to lsb. multibyte data transfers in msb-first format start with an instruction byte that includes the register address of the most significant data byte. subsequent data bytes should follow from high address to low address. in msb-first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communication cycle. when lsb-first = 1 (lsb-first) the instruction and data bit must be written from lsb to msb. multibyte data transfers in lsb-first format start with an instruction byte that includes the register address of the least significant data byte followed by mul- tiple data bytes. the serial port internal byte address generator increments for each byte of the multibyte communication cycle. the serial port controller data address decrements from the data address written toward 0x00 for multibyte i/o operations if the msb-first mode is active. the serial port controller address increments from the data address written toward 0x1f for multibyte i/o operations if the lsb-first mode is active. r/w n1 n0 a4 a3 a2 a1 a0 d7 d6 n d5 n d0 0 d1 0 d2 0 d3 0 d7 d6 n d5 n d0 0 d1 0 d2 0 d3 0 instruction cycle data transfer cycle csb sclk sdio sdo 05361-050 figure 53. serial register interface timing msb-first a0 a1 a2 a3 a4 n0 n1 r/w d0 0 d1 0 d2 0 d7 n d6 n d5 n d4 n d0 0 d1 0 d2 0 d7 n d6 n d5 n d4 n instruction cycle data transfer cycle csb sclk sdio sdo 05361-051 figure 54. serial register interface timing lsb-first instruction bit 6 instruction bit 7 csb sclk sdio t ds t ds t dh t pwh t pwl t sclk 05361-052 figure 55. timing diagram for spi register write data bit n?1 data bit n csb sclk sdio sdo t dv 05361-053 figure 56. timing diagram for spi register read
ad9776/ad9778/ad9779 rev. a | page 27 of 56 spi register map table 11. register name address bit 7 bit 6 bit 5 bi t 4 bit 3 bit 2 bit 1 bit 0 def. comm 0x00 00 sdio bidirectional lsb/msb first software reset power- down mode auto power- down enable pll lock indicator (read only) 0x00 0x01 01 filter interpolation factor<1:0 > filter modulation mode<3:0> zero stuffing enable 0x00 digital control 0x02 02 data format dual/interleaved data bus mode real mode data clock delay enable inverse sinc enable dataclk invert txenable invert q first 0x00 sync control 0x03 03 data clock delay mode<1:0> data clock divide ratio<1:0> reserved 0x00 0x04 04 data clock delay<3:0> output sync pulse divide<2:0> sync out delay<4> 0x00 0x05 05 sync out delay<3:0> input sync pulse frequency ratio<2:0> sync input delay<4> 0x00 0x06 06 sync input delay<3:0> input sync pulse timing error tolerance<3:0> 0x00 0x07 07 sync receiver enable sync driver enable sync triggering edge dac clock offset<4:0> 0x00 pll control 0x08 08 pll band select<5:0> pll vco agc gain<1:0> 0xcf 0x09 09 pll enable pll vco divider ratio<1:0> pll loop divide ratio<1:0> pll bias setting<2:0> 0x37 misc control 0x0a 10 pll control voltage range<2:0> (read only) pll loop bandwidth adjustment<4:0> 0x38 0x0b 11 i dac gain adjustment<7:0> 0xf9 i dac control register 0x0c 12 i dac sleep i dac power down i dac gain adjustment<9:8> 0x01 0x0d 13 auxiliary dac1 data<7:0> 0x00 aux dac1 control register 0x0e 14 auxiliary dac1 sign auxiliary dac1 current direction auxiliary dac1 power- down auxiliary dac1 data<9:8> 0x00 0x0f 15 q dac gain adjustment<7:0> 0xf9 q dac control register 0x10 16 q dac sleep q dac power- down q dac gain adjustment<9:8> 0x01 0x11 17 auxiliary dac2 data<7:0> 0x00 0x12 18 auxiliary dac2 sign auxiliary dac2 current direction auxiliary dac2 power- down auxiliary dac2 data<9:8> 0x00 aux dac2 control register 0x13 to 0x18 19 to 24 reserved 0x19 25 sync delay irq sync delay irq enable internal sync loopback 0x00 interrupt register 0x1a to 0x1f 26 to 31 reserved
ad9776/ad9778/ad9779 rev. a | page 28 of 56 table 12. spi register description address register name reg. no. bits description function default comm register 00 7 sdio bidirectional 0: use sdio pin as input data only 0 1: use sdio as bot h input and output data 00 6 lsb/msb first 0: first bit of se rial data is msb of data byte 0 1: first bit of serial data is lsb of data byte 00 5 software reset bit must be written with a 1, then 0 to soft reset spi register map 0 00 4 power-down mode 0: all circuitry is active 1: disable all digital and analog circuitry, only spi port is active 00 3 auto power-down enable controls auto power-down mode, see the power-down and sleep modes section 0 00 1 pll lock (read only) 0: pll is not locked 1: pll is locked 0 digital control register 01 7:6 filter interpolation factor 00: 1 interpolation 00 01: 2 interpolation 10: 4 interpolation 11: 8 interpolation 01 5:2 filter modulation mode see table 21 for filter modes 0000 01 0 zero stuffing 0: zero stuffing off 0 1: zero stuffing on 02 7 data format 0: signed binary 0 1: unsigned binary 02 6 dual/interleaved data bus mode 0: both input data ports receive data 0 1: data port 1 only receives data 02 5 real mode 0: enable q path for signal processing 0 1: disable q path data (internal q channel clocks disabled, i and q modulators disabled) 02 4 dataclk delay enable see the using data delay to meet timing requirements section. 02 3 inverse sinc enable 0: inverse sinc filter disabled 0 1: inverse sinc filter enabled 02 2 dataclk invert 0: output dataclk same phase as internal capture clock 0 1: output dataclk opposite phase as internal capture clock 02 1 txenable invert inverts the function of txenable pin 39, see the interleaved data mode section 0 02 0 q first 0: first byte of data is always i data at beginning of transmit 1: first byte of data is always q data at beginning of transmit sync control register 03 7:6 data clock delay mode 00: manual 00 03 5:4 extra data clock divide ratio data clock output divider (see table 22 for divider ratio) 00 03 3:0 reserved 000 04 7:4 data clock delay sets delay of refclk in to dataclk out 0000 04 3:1 output sync pulse divide se ts frequency of sync_o pulses 000 04 0 sync out delay sync output delay, bit 4 05 7:4 sync out delay sync output delay, bits<3:0> 0 05 3:1 input sync pulse frequency input sync pulse frequency divider, see the an-822 application note 000 05 0 sync input delay sync input delay, bit 4 0
ad9776/ad9778/ad9779 rev. a | page 29 of 56 address register name reg. no. bits description function default sync control register 06 7:4 sync input delay see the multiple dac synchronization section for details on using these registers to synchronize multiple dacs 0 06 3:0 input sync pulse timing error tolerance 0 07 7 sync receiver enable 0 07 6 sync driver enable 0 07 5 sync triggering edge 0 07 4:0 sync_i to input data sampling clock offset 0 pll control 08 7:2 pll band select vco frequency range vs. pll band select value (see table 18 ) 111001 08 1:0 vco agc gain control lower number (low gain) is generally better for performance 11 09 7 pll enable 0: pll off, dac rate clock supplied by outside source 0 1: pll on, dac rate clock synthesized internally from external reference clock via pll clock multiplier 09 6:5 pll vco divide ratio fvco/f dac 00 1 01 2 10 4 11 8 09 4:3 pll loop divide ratio f dac /f ref 00 2 01 4 10 8 11 16 09 2:0 pll bias setting always set to 010 010 0a 7:5 pll control voltage range 000 to 111, proportional to voltage at pll loop filter output, readback only misc control 0a 4:0 pll loop bandwidth adjustment see pll loop filter bandwidth section for details i dac control register 0b 7:0 i dac gain adjustment (7:0) lsb slice of 10-bit gain setting word for i dac 11111001 0c 7 i dac sleep 0: i dac on 0 1: i dac off 0c 6 i dac power-down 0: i dac on 0 1: i dac off 0c 1:0 i dac gain adjustment (9:8) msb slice of 10-bit gain setting word for i dac 01 0d 7:0 aux dac1 gain adjustment (7:0) lsb slice of 10-bit gain setting word for aux dac1 00000000 0e 7 aux dac1 sign 0: positive 1: negative 0e 6 aux dac1 current direction 0: source 0 1: sink 0e 5 aux dac1 power-down 0: aux dac1 on 0 1: aux dac1 off aux dac1 control register 0e 1:0 aux dac1 gain adjustment (9:8) msb slice of 10-bit gain setting word for aux dac1 00
ad9776/ad9778/ad9779 rev. a | page 30 of 56 address register name reg. no. bits description function default q dac control register 0f 7:0 q dac gain adjustment (7:0) lsb slice of 10-bit gain setting word for q dac 11111001 10 7 q dac sleep 0: q dac on 0 1: q dac off 10 6 q dac power-down 0: q dac on 0 1: q dac off 10 1:0 q dac gain adjustment (9:8) msb slice of 10-bit gain setting word for q dac 11 7:0 aux dac2 gain adjustment (7:0) lsb slice of 10-bit gain setting word for aux dac2 00000000 12 7 aux dac2 sign 0: positive 1: negative 12 6 aux dac2 current direction 0: source 0 1: sink 12 5 aux dac2 power-down 0: aux dac2 on 0 1: aux dac2 off aux dac2 control register 12 1:0 aux dac2 gain adjustment (9:8) msb slice of 10-bit gain setting word for aux dac2 00 interrupt register 19 7 0 19 6 sync delay irq readback, must write 0 to clear 0 19 5 0 19 3 0 19 2 sync delay irq enable 0 19 1 0 19 0 internal sync loopback 0
ad9776/ad9778/ad9779 rev. a | page 31 of 56 interpolation filter architecture the ad9776/ad9778/ad9779 can provide up to 8 interpola- tion, or the interpolation filters can be entirely disabled. it is important to note that the input signal should be backed off by approximately 0.01 db from full scale to avoid overflowing the interpolation filters. the coefficients of the low-pass filters and the inverse sinc filter are given in table 13 , tabl e 14 , table 15 , and table 16 . spectral plots for the filter responses are shown in figure 57 , figure 58 , and figure 59 . table 13. half-band filter 1 lower coefficient upper coefficient integer value h(1) h(55) ?4 h(2) h(54) 0 h(3) h(53) +13 h(4) h(52) 0 h(5) h(51) ?34 h(6) h(50) 0 h(7) h(49) +72 h(8) h(48) 0 h(9) h(47) ?138 h(10) h(46) 0 h(11) h(45) +245 h(12) h(44) 0 h(13) h(43) ?408 h(14) h(42) 0 h(15) h(41) +650 h(16) h(40) 0 h(17) h(39) ?1003 h(18) h(38) 0 h(19) h(37) +1521 h(20) h(36) 0 h(21) h(35) ?2315 h(22) h(34) 0 h(23) h(33) +3671 h(24) h(32) 0 h(25) h(31) ?6642 h(26) h(30) 0 h(27) h(29) +20,755 h(28) +32,768 table 14. half-band filter 2 lower coefficient upper coefficient integer value h(1) h(23) ?2 h(2) h(22) 0 h(3) h(21) +17 h(4) h(20) 0 h(5) h(19) ?75 h(6) h(18) 0 h(7) h(17) +238 h(8) h(16) 0 h(9) h(15) ?660 h(10) h(14) 0 h(11) h(13) +2530 h(12) +4096 table 15. half-band filter 3 lower coefficient upper coefficient integer value h(1) h(15) ?39 h(2) h(14) 0 h(3) h(13) +273 h(4) h(12) 0 h(5) h(11) ?1102 h(6) h(10) 0 h(7) h(9) +4964 h(8) +8192 table 16. inverse sinc filter lower coefficient upper coefficient integer value h(1) h(9) +2 h(2) h(8) ?4 h(3) h(7) +10 h(4) h(6) ?35 h(5) +401 10 ?100 ?4 4 f out ( input data rate) attenuation (db) ?3?2?10123 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 05361-054 figure 57. 2 interpolation, low-pass response to 4 input data rate (dotted lines indica te 1 db roll-off) 10 ?100 ?4 4 f out ( input data rate) attenuation (db) ?3?2?10123 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 05361-055 figure 58. 4 interpolation, low-pass response to 4 input data rate (dotted lines indica te 1 db roll-off)
ad9776/ad9778/ad9779 rev. a | page 32 of 56 10 ?100 ?4 4 f out ( input data rate) attenuation (db) ?3?2?10123 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 05361-056 figure 59. 8 interpolation, low-pass response to 4 input data rate (dotted lines indica te 1 db roll-off) with the interpolation filter and modulator combined, the incoming signal can be placed anywhere within the nyquist region of the dac output sample rate. when the input signal is complex, this architecture allows modulation of the input signal to positive or negative nyquist regions (see table 17 ). the nyquist regions of up to 4 the input data rate can be seen in figure 60 . ?4 ?8 ?3 ?6 ?2 ?4 ?1 ?2 dc 1 1 3 2 5 3 7 ?7 ?5 ?3 ?1 2 4 6 8 4 05361-057 figure 60. nyquist zones figure 57 , figure 58 , and figure 59 show the low-pass response of the digital filters with no modulation. by turning on the modulation feature, the response of the digital filters can be tuned to anywhere within the dac bandwidth. as an example, figure 61 to figure 67 show the nonshifted mode filter responses (refer to table 1 7 for shifted/nonshifted mode filter responses). 10 ?100 ?4 4 ?3?2?10123 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 f out ( input data rate) attenuation (db) 05361-058 figure 61. interpolation/modulation combination of 4 f dac /8 filter 10 ?100 ?4 4 ?3?2?10123 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 f out ( input data rate) attenuation (db) 05361-059 figure 62. interpolation/modulation combination of ?3 f dac /8 filter 10 ?100 ?4 4 ?3?2?10123 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 f out ( input data rate) attenuation (db) 05361-060 figure 63. interpolation/modulation combination of ?2 f dac /8 filter 10 ?100 ?4 4 ?3?2?10123 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 f out ( input data rate) attenuation (db) 05361-061 figure 64. interpolation/modulation combination of ?1 f dac /8 filter
ad9776/ad9778/ad9779 rev. a | page 33 of 56 10 ?100 ?4 4 ?3?2?10123 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 f out ( input data rate) attenuation (db) 05361-062 figure 65. interpolation/modulation combination of f dac /8 filter 10 ?100 ?4 4 ?3 ?2 ?1 0 1 2 3 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 f out ( input data rate) attenuation (db) 05361-063 figure 66. interpolation/modulation combination of 2 f dac /8 filter in shifted mode 10 ?100 ?4 4 ?3?2?10123 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 f out ( input data rate) attenuation (db) 05361-064 figure 67. interpolation/modulation combination of 3 f dac /8 filter in shifted mode shifted mode filter responses allow the pass band to be centered around 0.5 f data , 1.5 f data , 2.5 f data , and 3.5 f data . switching to the shifted mode response does not modulate the signal. instead, the pass band is simply shifted. for example, picture the response shown in figure 67 and assume the signal in-band is a complex signal over the bandwidth 3.2 f data to 3.3 f data . if the even mode filter response is then selected, the pass band becomes centered at 3.5 f data . however, the signal remains at the same place in the spectrum. the shifted mode capability allows the filter pass band to be placed anywhere in the dac nyquist bandwidth. the ad9776/ad9778/ad9779 are dual dacs with internal complex modulators built into the interpolating filter response. in dual channel mode, the devices expect the real and the imaginary components of a complex signal at digital input port 1 and digital input port 2 (i and q, respectively). the dac outputs then represent the real and imaginary components of the input signal, modulated by the complex carrier f dac /2, f dac /4, or f dac /8. with register 2, bit 6 set, the device accepts interleaved data on port 1 in the i, q, i, q . . . sequence. note that in interleaved mode, the channel data rate at the beginning of the i and the q data paths are now half the input data rate because of the inter- leaving. the maximum input data rate is still subject to the maximum specification of the device. this limits the synthesis bandwidth available at the input in interleaved mode. with register 0x02, bit 5 (real mode) set, the q channel and the internal i and q digital modulation are turned off. the output spectrum at the i dac then represents the signal at digital input port 1, interpolated by 1, 2, 4, or 8. the general recommendation is that if the desired signal is within 0.4 f data , the odd filter mode should be used. outside of this, the even filter mode should be used. in any situation, the total bandwidth of the signal should be less than 0.8 f data .
ad9776/ad9778/ad9779 rev. a | page 34 of 56 table 17. interpolation filter modes, (register 0x01, bits<5:2>) interpolation factor <7:6> filter mode <5:2> modulation nyquist zone pass band f_low 1 center 1 f_high 1 comments 8 0x00 dc 1 ?0.05 0 +0.05 8 0x01 dc shifted 2 0.0125 0.0625 0.1125 8 0x02 f/8 3 0.075 0.125 0.175 8 0x03 f/8 shifted 4 0.1375 0.1875 0.2375 8 0x04 f/4 5 0.2 0.25 0.3 8 0x05 f/4 shifted 6 0.2625 0.3125 0.3625 8 0x06 3f/8 7 0.325 0.375 0.425 8 0x07 3f/8 shifted 8 0.3875 0.4375 0.4875 8 0x08 f/2 ?8 ?0.55 ?0.5 ?0.45 8 0x09 f/2 shifted ?7 ?0.4875 ?0.4375 ?0.3875 8 0x0a ?3f/8 ?6 ?0.425 ?0.375 ?0.343 8 0x0b ?3f/8 shifted ?5 ?0.3625 ?0.3125 ?0.2625 8 0x0c ?f/4 ?4 ?0.3 ?0.25 ?0.2 8 0x0d ?f/4 shifted ?3 ?0.2375 ?0.1875 ?0.1375 8 0x0e ?f/8 ?2 ?0.175 ?0.125 ?0.075 8 0x0f ?f/8 shifted ?1 ?0.1125 ?0.0625 ?0.0125 in 8 interpolation; bw (min) = 0.0375 f dac bw (max) = 0.1 f dac 4 0x00 dc 1 ?0.1 0 +0.1 4 0x01 dc shifted 2 0.025 0.125 0.225 4 0x02 f/4 3 0.15 0.25 0.35 4 0x03 f/4 shifted 4 0.275 0.375 0.475 4 0x04 f/2 ?4 ?0.6 ?0.5 ?0.4 4 0x05 f/2 shifted ?3 ?0.475 ?0.375 ?0.275 4 0x06 ?f/4 ?2 ?0.35 ?0.25 ?0.15 4 0x07 ?f/4 shifted ?1 ?0.225 ?0.125 ?0.025 in 4 interpolation; bw (min) = 0.075 f dac bw (max) = 0.2 f dac 2 0x00 dc 1 ?0.2 0 +0.2 2 0x01 dc shifted 2 0.05 0.25 0.45 2 0x02 f/2 ?2 ?0.7 ?0.5 ?0.3 2 0x03 f/2 shifted ?1 ?0.45 ?0.25 ?0.05 in 2 interpolation; bw (min) = 0.15 f dac bw (max) = 0.4 f dac 1 frequency normalized to f dac .
ad9776/ad9778/ad9779 rev. a | page 35 of 56 interpolation filter minimum and maximum bandwidth specifications the ad977x uses a novel interpolation filter architecture that allows dac if frequencies to be generated anywhere in the spectrum. figure 68 shows the traditional choice of dac if output bandwidth placement. note that there are no possible filter modes in which the carrier can be placed near 0.5 f data , 1.5 f data , 2.5 f data , and so on. 10 ?80 ?4 4 f out ( input data rate), assuming 8 interpolation attenuation (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?3?2?10123 + f dac /2 + f dac /4 + f dac /8 baseband ? f dac /8 ? f dac /4 ? f dac /2 05361-065 figure 68. traditional bandwidt h options for txdac output if the filter architecture not only allows the interpolation filter pass bands to be centered in the middle of the input nyquist zones (as explained in this section), but also allows the possi- bility of a 3 f dac /8 modulation mode. with all of these filter combinations, a carrier of given bandwidth can be placed anywhere in the spectrum and fall into a possible pass band of the interpolation filters. the possible bandwidths accessible with the filter architecture are shown in figure 69 and figure 70 . note that the shifted and nonshifted filter modes are all accessible by programming the filter mode for the particular interpolation rate. 10 ?80 ?4 4 f out ( input data rate), assuming 8 interpolation attenuation (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?3 ?2 ?1 0 1 2 3 ? f dac /2 ?3 f dac /8 ? f dac /4 ? f dac /8 baseband + f dac /8 + f dac /4 +3 f dac /8 + f dac /2 05361-066 figure 69. nonshifted bandwidths acce ssible with the filter architecture 10 ?80 ?4 4 f out ( input data rate), assuming 8 interpolation attenuation (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?3 ?2 ?1 0 1 2 3 shifted ?3 f dac /8 shifted ? f dac /4 shifted ? f dac /8 shifted ?dc shifted ?dc shifted ? f dac /8 shifted ? f dac /4 shifted ?3 f dac /8 05361-067 figure 70. shifted bandwidths accessible with the filter architecture with this filter architecture, a signal placed anywhere in the spectrum is possible. however, the signal bandwidth is limited by the input sample rate of the dac and the specific placement of the carrier in the spectrum. the bandwidth restriction resulting from the combination of filter response and input sample rate is often referred to as the synthesis bandwidth, since this is the largest bandwidth that the dac can synthesize. the maximum bandwidth condition exists if the carrier is placed directly in the center of one of the filter pass bands. in this case, the total 0.1 db bandwidth of the interpolation filters is equal to 0.8 f data . as table 17 shows, the synthesis band- width as a fraction of dac output sample rate drops by a factor of 2 for every doubling of interpolation rate. the minimum bandwidth condition exists, for example, if a carrier is placed at 0.25 f data . in this situation, if the nonshifted filter response is enabled, the high end of the filter response cuts off at 0.4 f data , thus limiting the high end of the signal bandwidth. if the shifted filter response is enabled instead, then the low end of the filter response cuts off at 0.1 f data , thus limiting the low end of the signal bandwidth. the minimum bandwidth specification that applies for a carrier at 0.25 f data is therefore 0.3 f data . the minimum bandwidth behavior is repeated over the spectrum for carriers placed at ( n 0.25) f data , where n is any integer. driving the refclk input the refclk input requires a low jitter differential drive signal. it is a pmos input differential pair powered from the 1.8 v supply, therefore, it is important to maintain the specified 400 mv input common-mode voltage. each input pin can safely swing from 200 mv p-p to 1 v p-p about the 400 mv common-mode voltage. while these input levels are not directly lvds-compatible, refclk can be driven by an offset ac-coupled lvds signal, as shown in figure 71 .
ad9776/ad9778/ad9779 rev. a | page 36 of 56 lvds_p_in clk+ 50 50 0.1 f 0.1 f lvds_n_in clk? v cm = 400mv 05361-068 figure 71. lvds refclk drive circuit if a clean sine clock is available, it can be transformer-coupled to refclk, as shown in figure 71 . use of a cmos or ttl clock is also acceptable for lower sample rates. it can be routed through a cmos to lvds translator, then ac-coupled, as described in this section. alternatively, it can be transformer- coupled and clamped, as shown in figure 72 . 50 50 ttl or cmos clk input clk+ clk? v cm = 400mv bav99zxct high speed dual diode 0.1 f 05361-069 figure 72. ttl or cmos refclk drive circuit a simple bias network for generating vcm is shown in figure 73 . it is important to use cvdd18 and cgnd for the clock bias circuit. any noise or other signal that is coupled onto the clock is multiplied by the dac digital input signal and can degrade dac performance. 0.1 f 1nf 1nf v cm = 400mv cvdd18 cgnd 1k 2 87 05361-070 figure 73. refclk vcm generator circuit internal pll clock multiplier/clock distribution the internal clock structure on the devices allows the user to drive the differential clock inputs with a clock at 1 or an integer multiple of the input data rate or at the dac output sample rate. an internal pll provides input clock multiplication and provides all the internal clocks required for the interpolation filters and data synchronization. the internal clock architecture is shown in figure 74 . the reference clock is the differential clock at pin 5 and pin 6. this clock input can be run differentially or singled-ended by driving pin 5 with a clock signal and biasing pin 6 to the midswing point of the signal at pin 5. the clock architecture can be run in the following configurations: pll enabled (register 0x09, bit 7 = 1) the pll enable switch shown in figure 74 is connected to the junction of the n1 dividers (pll vco divide ratio) and n2 dividers (pll loop divide ratio). divider n3 determines the interpolation rate of the dac, and the ratio n3/n2 determines the ratio of reference clock/input data rate. the vco runs optimally over the range of 1.0 ghz to 2.0 ghz, so that n1 keeps the speed of the vco within this range, although the dac sample rate can be lower. the loop filter components are entirely internal and no external compensation is necessary. pll disabled (register 0x09, bit 7 = 0) the pll enable switch shown in figure 74 is connected to the reference clock input. the differential reference clock input is the same as the dac output sample rate. n3 determines the interpolation rate. adc phase detection vco dac interpolation rate internal loop filter 0x0a (4:0) loop filter bandwidth reference clock (pins 5 and 6) 0x0a (7:5) pll control voltage range 0x08 (7:2) vco range 0x09 (7) pll enable internal dac sample rate clock dataclk out (pin 37) 0x01 (7:6) 0x09 (6:5) pll vco divide ratio 0x09 (4:3) pll loop divide ratio n3 n2 n1 05361-071 figure 74. internal clock architecture
ad9776/ad9778/ad9779 rev. a | page 37 of 56 table 18. vco frequency range vs. pll band select value typical pll lock ranges vco frequency range in mhz typ at 25c typ over temp pll band select f low f high f low f high 111111 (63) auto mode auto mode 111110 (62) 2056 2170 2105 2138 111101 (61) 2002 2113 2048 2081 111100 (60) 1982 2093 2029 2061 111011 (59) 1964 2075 2010 2043 111010 58) 1947 2057 1992 2026 111001 (57) 1927 2037 1971 2006 111000 (56) 1907 2016 1951 1986 110111 (55) 1894 2003 1936 1972 110110 (54) 1872 1981 1913 1952 110101 (53) 1852 1960 1892 1931 110100 (52) 1841 1948 1881 1920 110011 (51) 1816 1923 1855 1895 110010 (50) 1796 1903 1835 1874 110001 (49) 1789 1895 1828 1867 110000 (48) 1764 1871 1803 1844 101111 (47) 1746 1853 1784 1826 101110 (46) 1738 1842 1776 1815 101101 (45) 1714 1820 1752 1794 101100 (44) 1700 1804 1737 1779 101011 (43) 1689 1790 1726 1764 101010 (42) 1657 1757 1695 1734 101001 (41) 1641 1738 1679 1714 101000 (40) 1610 1707 1649 1684 100111 (39) 1597 1689 1635 1666 100110 (38) 1568 1661 1607 1639 100101 (37) 1553 1641 1592 1617 100100 (36) 1525 1613 1562 1592 100011 (35) 1511 1595 1548 1572 100010 (34) 1484 1570 1519 1549 100001 (33) 1470 1552 1506 1528 100000 (32) 1441 1525 1474 1504 011111 (31) 1429 1509 1463 1487 011110 (30) 1403 1485 1433 1464 011101 (29) 1390 1469 1422 1447 011100 (28) 1362 1443 1391 1423 011011 (27) 1352 1429 1380 1407 011010 (26) 1325 1405 1352 1385 011001 (25) 1314 1390 1340 1369 011000 (24) 1290 1368 1315 1350 010111 (23) 1276 1351 1302 1332 010110 (22) 1253 1331 1277 1313 010101 (21) 1239 1313 1264 1295 010100 (20) 1183 1255 1205 1240 010011 (19) 1204 1275 1227 1259 010010 (18) 1151 1221 1172 1207 010001 (17) 1171 1240 1193 1224 010000 (16) 1148 1218 1170 1204 001111 (15) 1137 1204 1159 1189 typical pll lock ranges vco frequency range in mhz typ at 25c typ over temp pll band select f low f high f low f high 001110 (14) 1116 1184 1137 1170 001101 (13) 1106 1171 1127 1157 001100 (12) 1086 1152 1106 1138 001011 (11) 1075 1138 1095 1124 001010 (10) 1055 1119 1075 1106 001001 (9) 1045 1107 1065 1093 001000 (8) 1027 1090 1047 1076 000111 (7) 1016 1076 1034 1062 000110 (6) 998 1059 1016 1046 000101 (5) 987 1046 1005 1032 000100 (4) 960 1017 977 1004 000011 (3) 933 989 949 976 000010 (2) 908 962 923 950 000001 (1) 883 936 898 925 000000 (0) 859 911 873 899 vco frequency ranges because the pll band covers greater than a 2 frequency range, there can be two options for the pll band select: one at the low end of the range and one at the high end of the range. under these conditions, the vco phase noise is optimal when the user selects the band select value corresponding to the high end of the frequency range. figure 75 shows how the vco bandwidth and the optimal vco frequency varies with the band select value. vco frequency ranges over temperature the specifications given over temperature in table 18 are for a single part in a single lot. part-to-part, and lot-to-lot, these specifications can exhibit a mean shift of several register settings. systems should be designed to take this potential shift into account to maintain optimal pll performance. pll loop filter bandwidth the loop filter bandwidth of the pll is programmed via spi register 0x0a, bits<4:0>. changing these values switches capacitors on the internal loop filter. no external loop filter components are required. this loop filter has a pole at 0 (p1), and then a zero (z1) pole (p2) combination. z1 and p2 occur within a decade of each other. the location of the zero pole is determined by bits<4:0>. for a setting of 00000, the zero pole occurs near 10 mhz. by setting bits<4:0> to 11111, the z1/p2 combination can be lowered to approximately 1 mhz. the relationship between bits<4:0> and the position of the zero pole between 1 mhz and 10 mhz is linear. the internal components are not low tolerance, however, and can drift by as much as 30%. for optimal performance, the bandwidth adjustment (register 0x0a, bits<4:0>) should be set to 11111 for all operating modes with pll enabled. the pll bias settings
ad9776/ad9778/ad9779 rev. a | page 38 of 56 (register 0x09, bits<2:0>) should be set to 111. the pll control voltage (register 0x0a, bits<7:5>) is read back and is propor- tional to the dc voltage at the internal loop filter output. with the pll bias settings given in this section, the readback from the pll control voltage should typically be 010, or possibly 001 or 011. anything outside of this range indicates that the pll is not operating correctly. 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 850 2150 2050 1950 1850 1750 1650 1450 1550 1350 1250 1150 1050 950 f vco (mhz) pll band 05361-072 figure 75. typical pll band select vs. frequency at 25c 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 850 2150 2050 1950 1850 1750 1650 1450 1550 1350 1250 1150 1050 950 f vco (mhz) pll band 05361-113 figure 76. typical pll band select vs. frequency over temperature the ad977x has an autosearch feature that determines the optimal settings for the pll. to enable the autosearch mode, set register 0x08, bits<7:2> to 11111b, and read back the value from register 0x08, bits<7:2>. autosearch mode is intended to find the optimal pll settings only, after which the same settings should be applied in manual mode. it is not recommended that the pll be set to autosearch mode during regular operation. full-scale current generation internal reference full-scale current on the i dac and q dac can be set from 8.66 ma to 31.66 ma. initially, the 1.2 v band gap reference is used to set up a current in an external resistor connected to i120 (pin 75). a simplified block diagram of the reference circuitry is shown in figure 77 . the recommended value for the external resistor is 10 k, which sets up an i reference in the resistor of 120 a, which in turn provides a dac output full- scale current of 20 ma. because the gain error is a linear function of this resistor, a high precision resistor improves gain matching to the internal matching specification of the devices. internal current mirrors provide a current-gain scaling, where i dac or q dac gain is a 10-bit word in the spi port register (register 0x0a, register 0x0b, register 0x0e, and register 0x0f). the default value for the dac gain registers gives an i fs of approximately 20 ma, where i fs is equal to 32 1024 6 12 27 v2.1 ? ? ? ? ? ? ? ? ? ? ? ? + i dac dac full-scale reference current current scaling i dac gain q dac gain q dac ad9779 vref 10k 1.2v band gap 0.1 f i120 05361-073 figure 77. reference circuitry 35 0 0 1000 dac gain code i fs (ma) 30 25 20 15 10 5 200 400 600 800 05361-074 figure 78. i fs vs. dac gain code application of auxiliary da cs in single sideband transmitter two auxiliary dacs are provided on the ad977x. the full-scale output current on these dacs is derived from the 1.2 v band gap reference and external resistor. the gain scale from the ref- erence amplifier current i reference to the auxiliary dac reference current is 16.67 with the auxiliary dac gain set to full scale (10-bit values, spi register 0x0d and spi register 0x11), this gives a full-scale current of approximately 2 ma for auxiliary dac1 and auxiliary dac2. the auxiliary dac outputs are not differential. only one side of the auxiliary dac (p or n) is active at one time. the inactive side goes into a high impedance state (>100 k). in addition, the p or n outputs can act as current sources or sinks. the control of the p and n side for both auxiliary dacs is via register 0x0e and register 0x10, bits<7:6>. when sourcing current, the output compliance
ad9776/ad9778/ad9779 rev. a | page 39 of 56 voltage is 0 v to 1.6 v. when sinking current, the output compliance voltage is 0.8 v to 1.6 v. the auxiliary dacs can be used for local oscillator (lo) cancella- tion when the dac output is followed by a quadrature modulator. this lo feedthrough is caused by the input referred dc offset voltage of the quadrature modulator (and the dac output offset voltage mismatch) and can degrade system performance. typical dac-to-quadrature modulator interfaces are shown in figure 79 and figure 80 . often, the input common-mode voltage for the modulator is much higher than the output compliance range of the dac, so that ac coupling or a dc level shift is necessary. if the required common-mode input voltage on the quadrature modulator matches that of the dac, then the dc blocking capacitors in figure 79 can be removed. a low-pass or band-pass passive filter is recommended when spurious signals from the dac (distortion and dac images) at the quadrature modulator inputs can affect the system performance. placing the filter at the location shown in figure 79 and figure 80 allows easy design of the filter, as the source and load impedances can easily be designed close to 50 . 05361-115 ad9779 q dac ad9779 aux dac2 25 to 50 0.1 f 0.1 f optional passive filtering quadrature modulator v+ quad mod q inputs ad9779 i dac ad9779 aux dac1 25 to 50 0.1 f 0.1 f optional passive filtering quadrature modulator v+ quad mod i inputs figure 79. typical use of auxiliary dacs ac coupling to quadrature modulator 05361-116 ad9779 i or q dac ad9779 aux dac1 or 2 25 to 50 25 to 50 optional passive filtering quadrature modulator v+ quad mod i or q inputs figure 80. typical use of auxiliary dacs dc coupling to quadrature modulator with dc shift power dissipation figure 81 to figure 89 show the power dissipation of the 1.8 v and 3.3 v digital and clock supplies in single dac and dual dac modes. in addition to this, the power dissipation/current of the 3.3 v supply (mode and speed independent) in single dac mode is 102 mw/31 ma. in dual dac mode, this is 182 mw/5 5 ma. furthermore, when the pll is enabled, it adds 90 mw/50 ma to the 1.8 v clock supply regardless of the mode of the ad9779. 0 0 250 f data (msps) power (w) 0.6 0.7 0.5 0.4 0.3 0.2 0.1 25 50 75 100 125 150 175 200 225 8 interpolation, zero stuffing 8 interpolation 4 interpolation 4 interpolation, zero stuffing 2 interpolation 1 interpolation 2 interpolation, zero stuffing 1 interpolation, zero stuffing 05361-076 figure 81. total power dissipation, i data only, real mode 0 0 250 f data (msps) power (w) 0.4 25 50 75 100 125 150 175 200 225 8 interpolation 4 interpolation 2 interpolation 1 interpolation 0.3 0.2 0.1 05361-078 figure 82. power dissipation, digital 1. 8 v supply, i data only, real mode, does not include zero stuffing 0 0 250 f data (msps) power (w) 0.08 25 50 75 100 125 150 175 200 225 8 interpolation 4 interpolation 2 interpolation 1 interpolation 0.06 0.04 0.02 05361-079 figure 83. power dissipati on, clock 1.8 v supply, i data only, real mode, includes modulation modes, does not include zero stuffing
ad9776/ad9778/ad9779 rev. a | page 40 of 56 0 0 250 f data (msps) power (w) 0.075 25 50 75 100 125 150 175 200 225 0.050 0.025 all interpolation modes 05361-080 figure 84. digital 3.3 v supply, i data only, real mode, includes modulation modes and zero stuffing 0 0 300 250 275 f data (msps) power (w) 0.6 1.0 0.7 0.8 0.9 0.5 0.4 0.3 0.2 0.1 25 50 75 100 125 150 175 200 225 05361-077 1 interpolation 1 interpolation, zero stuffing 2 interpolation, all modulation modes 2 interpolation, zero stuffing 4 interpolation, all modulation modes 4 interpolation, zero stuffing 8 interpolation, all modulation modes 8 interpolation, zero stuffing figure 85. total power dissipation, dual dac mode 0 0 250 f data (msps) power (w) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 25 50 75 100 125 150 175 200 225 2 interpolation 4 interpolation 1 interpolation, no modulation 8 interpolation, f dac /8, f dac /4, f dac /2, no modulation 05361-081 figure 86. power dissipati on, digital 1.8 v supply, i and q data, dual dac mode, does not include zero stuffing 0 0 250 f data (msps) power (w) 0.125 25 50 75 100 125 150 175 200 225 2 interpolation 4 interpolation 1 interpolation, no modulation 8 interpolation, f dac /8, f dac /4, f dac /2, no modulation 0.100 0.075 0.050 0.025 05361-082 figure 87. power dissipati on, clock 1.8 v supply, i and q data, dual dac mode, does not include zero stuffing 0 0 250 f data (msps) power (w) 0.075 25 50 75 100 125 150 175 200 225 0.050 0.025 all interpolation modes 05361-083 figure 88. digital 3.3 v supply, i and q data, dual dac mode 0.16 0 0 1200 f dac (msps) power (w) 0.14 0.12 0.10 0.08 0.06 0.04 0.02 200 400 600 800 1000 05361-084 figure 89. power dissipation of inverse sinc filter
ad9776/ad9778/ad9779 rev. a | page 41 of 56 power-down and sleep modes interleaved data mode the ad977x has a variety of power-down modes, so that the digital engine, main txdacs, or auxiliary dacs can be powered down individually or together. via the spi port, the main txdacs can be placed in sleep or power-down mode. in sleep mode, the txdac output is turned off, thus reducing power dissipation. the reference remains powered on, however, so that recovery from sleep mode is very fast. with the power-down mode bit set (register 0x00, bit 4), all analog and digital circuitry, including the reference, is powered down. the spi port remains active in this mode. this mode offers more substantial power savings than sleep mode, but the turn-on time is much longer. the auxiliary dacs also have the capability to be programmed into sleep mode via the spi port. the auto power-down enable bit (register 0x00, bit 3) controls the power-down function for the digital section of the devices. the auto power-down function works in conjunction with the txenable pin (pin 39) according to the following: the txenable bit is dual function. in dual port mode, it is simply used to power down the digital section of the devices. in interleaved mode, the iq data stream is synchronized to txenable. therefore, to achieve iq synchronization, txenable should be held low until an i data word is present at the inputs to data port 1. if a dataclk rising edge occurs while txenable is at a high logic level, iq data becomes synchronized to the dataclk output. txenable can remain high and the input iq data remains synchronized. to be backwards-compatible with previous dacs from analog devices, inc. such as the ad9777 and ad9786, the user can also toggle txenable once during each data input cycle, thus continually updating the synchronization. if txenable is brought low and held low for multiple refclk cycles, then the devices flush the data in the interpolation filters, and shut down the digital engine after the filters are flushed. the amount of refclk cycles it takes to go into this power-down mode is then a function of the length of the equivalent 2, 4, or 8 interpolation filter. the timing of txenable, i/q select, filter flush, and digital power-down are shown in figure 91 . txenable (pin 39) = 0: autopower-down enable = 0: flush data path with 0s 1: flush data for multiple refclk cycles; then automatically place the digital engine in power-down state. dacs, reference, and spi port are not affected. interleaved input data txenable can remain high or toggle for i/q synchronization i1 q1 i2 q2 txenable flushing interpolation filters power down digital section 05361-085 or txenable (pin 39) = 1: normal operation as shown in figure 90 , the power dissipation saved by using the power down mode is nearly proportional to the duty cycle of the signal at the txenable pin. figure 91. txenable function the txenable function can be inverted by changing the status of register 0x02, bit 1. the other bit that controls iq ordering is the q-first bit (register 0x02, bit 0). with the q-first bit reset to the default of 0, the iq pairing that is latched is the i1q1, i2q2, and so on. with iq first set to 1, the first i data is discarded and the pairing is i2q1, i3q2, and so on. note that with iq-first set, the i data is still routed to the internal i channel, the q data is routed to the internal q channel, and only the pairing changes. 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 100 80 60 40 20 duty cycle (%) power savings 05361-119 2 int f data = 50msps 8 int f data = 50msps 2 int f data = 200msps 4 int f data = 50msps 4 int f data = 200msps 8 int f data = 200msps timing information figure 92 to figure 95 show some of the various timing possibilities when the pll is enabled. the combination of the settings of n2 and n3 from figure 74 means that the reference clock frequency can be a multiple of the actual input data rate. figure 92 to figure 95 show, respectively, what the timing looks like when n2/n3 = 1 and 2. figure 90. power savings based on duty cycle of txenable if the txenable invert bit (register 0x02, bit 1) is set, the function of this txenable pin is inverted. in interleaved mode, set-up and hold times of dataclk out to data in are the same as those shown in figure 92 to figure 95 . it is recommended that any toggling of txenable occur concurrently with the digital data input updating. in this way, timing margins between dataclk, txenable, and digital input data are optimized.
ad9776/ad9778/ad9779 rev. a | page 42 of 56 05361-120 reference clock in data clock out input data t srefclk t hrefclk t sdataclk t hdataclk figure 92. timing specifications, pll enabled or disabled, interpolation = 1 reference clock in data clock out sync_in t s_sync t h_sync 05361-121 input data t srefclk t hrefclk t sdataclk t hdataclk figure 93. timing specifications, pll enabled or disabled, interpolation = 2 0 5361-122 reference clock in data clock out input data t srefclk t hrefclk t sdataclk t hdataclk t s_sync t h_sync sync_in figure 94. timing specifications, pll enabled or disabled, interpolation = 4 reference clock in data clock out 05361-123 input data t srefclk t hrefclk t sdataclk t hdataclk sync_in t s_sync t h_sync figure 95. timing specifications, pll enabled or disabled, interpolation = 8
ad9776/ad9778/ad9779 rev. a | page 43 of 56 specifications are given in tabl e 19 for the drift of input data set up and hold time vs. temperature, as well as the data keep out window (kow). note that although these specifications do drift, the length of the keep out window, where input data is invalid, changes very little over temperature. table 19. ad9779 timing spec ifications vs. temperature timing parameter temperature min t s (ns) min t h (ns) max kow (ns) refclk to data ?40c ?0.8 +2.2 +1.3 +25c ?1.1 +2.5 +1.4 +85c ?1.3 +2.9 +1.5 dataclk to data ?40c +1.8 ?0.4 +1.3 +25c +2.1 ?0.7 +1.4 +85c +2.5 ?0.9 +1.5 sync_i to refclk ?40c to +85c ?0.2 +1.0 +0.8 synchronization of input data to dataclk output (pin 37) synchronizing the input data bus to the dataclk out signal is achieved by meeting the timing relationships between dataclk and data timing specified in table 19 . if the user is synchro- nizing the input data to the dataclk out, the sync input (sync_i) signal does not need to be applied and can be ignored (connect to gnd). synchronization of input data to the refclk input (pin 5 and pin 6) with pll enabled or disabled synchronizing the input data bus to the refclk input requires the use of the sync_i input pins (pin 13 and pin 14). if the sync_i input is not used, there is a phase ambiguity between the dataclk out and the refclk in. this ambiguity matches the interpolation rate in which the ad9779, for example, is currently operating. because input data is latched on the rising edge of dataclk, it is impossible for the user to determine onto which one of the multiple internal dacclk edges (as an example, one of four edges in 4 interpolation) the input data actually latches. for the user to specifically determine the exact edge of refclk on which the data is being latched, a rising edge must be periodically applied to sync_i. the frequency of the sync_i signal must be equal to f dac /2 n , n being an integer, and must be no greater than dataclk for proper synchronization. there is no limit on how slow the sync_i signal can be driven. as long as the set up and hold timing relationship between sync_i and refclk given in tabl e 19 is met, the input data is latched on the immediate next rising edge of refclk. note that a rising edge of dataclk out occurs concurrently with the next refclk rising edge, after a short propagation delay. although this propagation delay is not specified, input data setup and hold timing information is given with respect to refclk in and dataclk out in figure 92 to figure 95 . also, note that in 1 interpolation, because there is no phase ambiguity, there is no need to use the sync_i signal. valid timing window in addition to the timing requirements of sync_i with respect to refclk, it is important to understand that the valid timing window for sync_i is limited by the internal dac sample rate. this is shown in figure 96 . when the t s and t h requirements are met, the valid timing window for sync_i extends only as far as one period of the internal dac sample rate (minus t s and t h ). failure to meet this timing specification can potentially result in erroneous data being latched into the ad9779 digital inputs. as an example, if the ad9779 input data rate is 122.88 msps and the refclk is the same, with the ad9779 in 4 interpola- tion, the dac sample rate is 1/491.52 mhz or about 2 ns. with a t s of ?0.2 ns and t h of 1.0 ns, this gives a valid timing window for sync_i of 2 ns ? 0.8 ns = 1.2 ns the timing window of the digital input data to refclk can be moved in increments of one internal refclk cycle by using the refclk offset register (register 0x7, bits<4:0>). because sync_i can be run at the same frequency as refclk when the pll is enabled, best practice suggests that in this con- dition, refclk and sync_i originate from the same source. this limits the variation in time between these two signals and makes the overall timing budget easier to achieve. a slight delay may be necessary on the refclk path in this configuration to add more timing margin between refclk and sync_i (see table 19 for timing relationship). 0 5361-124 refcl k sync_i t s t h t dac_sample t dac_sample figure 96. valid timing relationship for sync_i to refclk
ad9776/ad9778/ad9779 rev. a | page 44 of 56 using data delay to meet timing requirements to meet strict timing requirements at input data rates of up to 250 msps, the ad977x has a fine timing feature. fine timing adjustments are made by programming values into the data clock delay register (register 0x04, bits<7:4>). this register can be used to add delay between the refclk in and the dataclk out. figure 97 shows the default delay present when dataclk delay is disabled. the disable function bit is found in register 0x02, bit 4. figure 98 shows the delay present when dataclk delay is enabled and set to 0000. figure 99 indicates the delay when dataclk delay is enabled and set to 1111. note that the setup and hold times specified for data to dataclk are defined for dataclk delay disabled. ch1 1.00v tek run: 5.00gs/s sample ch2 500mv m2.00ns ch1 420mv : 4.48ns @: 40.28ns 2 1 05361-089 figure 97. delay from re fclk to dataclk with dataclk delay disabled ch1 1.00v tek run: 5.00gs/s sample ch2 500mv m2.00ns ch1 420mv : 4.76ns @: 35.52ns 2 1 05361-090 figure 98. delay from re fclk to dataclk out with dataclk delay = 0000 ch1 1.00v tek run: 5.00gs/s sample ch2 500mv m2.00ns ch1 420mv : 7.84ns @: 32.44ns 2 1 05361-091 figure 99. delay from re fclk to dataclk out with dataclk delay = 1111 the difference between the minimum delay shown in figure 98 and the maximum delay shown in figure 99 is the range programmable using the dataclk delay register. the delay (in absolute time) when programming dataclk delay between 0000 and 1111 is a linear extrapolation between these two figures. the typical delays per increment over temperature are shown in table 20 . table 20. data delay line typi cal delays over temperature delays 40c 25c 85c nit delay between disabled and enabled 370 416 432 ps average delay per increment 171 183 197 ps the frequency of dataclk out depends on several program- mable settings: interpolation, zero stuffing, and interleaved/ dual port mode, all of which have an effect on the refclk frequency. the divisor function between refclk and dataclk is equal to the values shown in table 21 . table 21. refclk to dataclk divisor ratio interpolation ero stuffing input mode divisor 1 disabled dual port 1 2 disabled dual port 2 4 disabled dual port 4 8 disabled dual port 8 1 disabled interleaved invalid 2 disabled interleaved 1 4 disabled interleaved 2 8 disabled interleaved 4 1 enabled dual port 2 2 enabled dual port 4 4 enabled dual port 8 8 enabled dual port 16 1 enabled interleaved 1 2 enabled interleaved 2 4 enabled interleaved 4 8 enabled interleaved 8
ad9776/ad9778/ad9779 rev. a | page 45 of 56 in addition to this divisor function, dataclk can be divided by up to an additional factor of 4, according to the state of the dataclk divide register (register 0x03, bits<5:4>). for more details, see tabl e 22 ). table 22. extra dataclk divisor ratio register 0x03, bits<5:4> divider ratio 00 1 01 2 10 4 11 1 the maximum divisor resulting from the combination of the values in tabl e 21 , and the dataclk divide register is 32. manual input timing correction correction of input timing can be achieved manually. the correction function is controlled by register 0x03, bits<7:6>. the function is programmed as shown in table 23 . table 23. input timing correction mode register 0x03, bits<7:6> function 00 error check disabled 01 reserved 10 reserved 11 reserved necessary corrections can be made by adjusting dataclk delay and the dataclk invert bit (register 2, bit 2). dataclk delay can then be swept to find the range over which the timing is valid. the final value for data delay should be the value that corresponds to the middle of the valid timing range. if a valid timing range is not found during this sweep, the user should invert the dataclk invert bit and repeat the process. multiple dac synchronization the ad9779 has programmable features that allow the cmos digital data bus inputs and internal filters on multiple devices to be synchronized. this means that the dataclk output signal on one ad9779 can be used to register the output data for a data bus delivering data to multiple ad9779s. the details of this opera- tion are given in the analog devices application note an-822 .
ad9776/ad9778/ad9779 rev. a | page 46 of 56 evaluation board operation the ad977x evaluation board is designed to optimize the dac performance and the speed of the digital interface, yet remains user friendly. to operate the board, the user needs a power source, a clock source, and a digital data source. the user also needs a spectrum analyzer or an oscilloscope to look at the dac output. the diagram in figure 100 illustrates the test setup. a sine or square wave clock works well as a clock source. the dc offset on the clock is not a problem, since the clock is ac-coupled on the evaluation board before the refclk inputs. all necessary connections to the evaluation board are shown in more detail in figure 101 . the evaluation board comes with software that allows the user to program the spi port. via the spi port, the devices can be programmed into any of its various operating modes. when first operating the evaluation board, it is useful to start with a simple configuration, that is, a configuration in which the spi port settings are as close as possible to the default settings. the default software window is shown in figure 102 . the arrows indicate which settings need to be changed for an easy first time evaluation. note that this implies that the pll is not being used and that the clock being used is at the speed of the dac output sample rate. for a more detailed description of how to use the pll, see the pll loop filter bandwidth section. digital pattern generator adapter cables clock generator ad9779 evaluation board clkin spi port dataclk out c lock in spectrum analyzer 1.8v power supply 3.3v power supply 05361-097 figure 100. typical test setup spi port ad9779 j1 clock in p4 digital input connector s7 dclkout aux33 dvdd18 dvdd33 cvdd18 avdd33 j2 5v supply analog devices ad9779/8/6 rev d s5 output 1 s6 output 2 ad8349 local osc input modulator output +5v gnd jp4 jp15 jp8 jp14 jp3 jp16 jp2 jp17 05361-098 figure 101. ad977x evaluation board showing all connections
ad9776/ad9778/ad9779 rev. a | page 47 of 56 1. set interpol a tion r a te 2. set interpolation filter mode 3. set input data format 4. set dataclk polarity to match input timing 0 5361-099 figure 102. spi port software window the default settings for the evaluation board allow the user to view the differential outputs through a transformer that converts the dac output signal to a single-ended signal. on the evaluation board, these transformers are designated t1a, t2a, t3a, and t4a. there are also four common-mode transformers on the board that are designated t1b, t2b, t3b, and t4b. the recommended operating setup places the transformer and common-mode transformer in series. a pair of transformers and common-mode transformers are installed on each dac output, so that the pairs can be set up in either order. as an example, for the frequency range of dc to 30 mhz, it is recommended that the transformer be placed right after the dac. above dac output frequencies of 30 mhz, it is recommended that the common-mode transformer is placed right after the dac outputs, followed by the transformer.
ad9776/ad9778/ad9779 rev. a | page 48 of 56 modifying the evaluation board to use the ad8349 on-board quadrature modulator the evaluation board contains an analog devices ad8349 quadrature modulator. the ad977x and ad8349 provide an easy-to-interface dac/modulator combination that can be easily evaluated on the evaluation board. to route the dac output signal to the quadrature modulator, the following jumper settings must be made: unsoldered: jp14, jp15, jp16, jp17 soldered: jp2, jp3, jp4, jp8 the dac output area of the evaluation board is shown in figure 103 . the jumpers that need to be changed to use the ad8349 are circled. also circled are the 5 v and gnd connections for the ad8349. 05361-100 figure 103. photo of evaluation board, dac output area
ad9776/ad9778/ad9779 rev. a | page 49 of 56 evaluation board schematics c69 0.1 f + cvdd18 tp2 black tp17 red tp1 red l1 exc-cl4532u1 l6 exc-cl4532u1 c68 0.1 f c77 22 f 16v cvdd18_in c66 0.1 f + vddm dgnd2 2 tp14 red tp15 black l12 exc-cl4532u1 l16 exc-cl4532u1 c67 0.1 f c46 22 f 16v vddm_in dgnd2 tp13 red r51 9k r52 10k r55 10k c26 0.1 f + avdd33 tp8 black tp19 red tp5 red l3 exc-cl4532u1 l13 exc-cl4532u1 c28 0.1 f c20 22 f 16v avdd33_in c49 0.1 f + dpwr33 tp10 black tp21 red tp7 red l5 exc-cl4532u1 l15 exc-cl4532u1 c48 0.1 f c22 22 f 16v dpwr33_in + c70 0.1 f dvdd18 tp4 black tp18 red tp3 red l2 exc-cl4532u1 l7 exc-cl4532u1 c71 0.1 f c76 22 f 16v dvdd18_in c42 0.1 f + dvdd33 tp9 black tp20 red tp6 red l4 exc-cl4532u1 l14 exc-cl4532u1 c45 0.1 f c21 22 f 16v dvdd33_in 3 u6 4 74ac14 11 u6 10 74ac14 9 u6 8 74ac14 5 u6 6 74ac14 2 u5 csb s1 swsecma s3 swsecma s2 swsecma 1 1 3 2 74ac14 spi_csb spi_clk spi_sdi spi_sdo 4 u5 3 74ac14 6 u5 5 74ac14 1 u6 2 74ac14 12 u5 13 74ac14 10 u5 11 74ac14 8 u5 9 74ac14 13 u6 12 74ac14 p1 1 2 3 4 5 6 r53 9k r54 9k sdi 1 3 2 sclk 1 3 2 s4 swsecma tp16 red tjak06rap class = io fci-68898 sdo 1 3 2 05361-101 figure 104. evaluation board, rev. d, power supply decoupling and spi interface
ad9776/ad9778/ad9779 rev. a | page 50 of 56 6 aux1_n aux1_p aux2_p clk_n clk_p dclk i120 iout1_n iout1_p iout1_n iout1_p iout2_p iout2_n iout2_p iout2_n iptat irq p1d0 p1d1 p1d10 p1d11 p1d12 p1d13 p1d14 p1d15 p1d2 p1d3 p1d4 p1d5 p1d6 tp12 red p1d7 p1d8 p1d9 p2d0 p2d1 p2d10 p2d11 p2d12 p2d13 p2d14 p2d15 p2d2 p2d3 p2d4 p2d5 p2d6 p2d0 p2d1 p2d2 p2d3 p2d4 p2d5 p2d6 p2d7 jp7 jp18 u11 u1 9779tqfp + c4 4.7f c29 1nf volt dvdd33 dvdd18 p2d8 p2d9 pad pll_lock reset spi_clk spi_csb spi_sdi spi_sdo spi_clk spi_csb spi_sdi spi_sdo sync_1n sync_1p sync_on sync_op vdd18_43 vdda33_76 vdda33_78 vdda33_80 vddc18_1 vddc18_10 vddc18_2 vddc18_9 vddd18_23 vddd18_33 vddd18_53 vddd18_60 vddd18 vddd33_38 vddd33_61 vref_74 vssa_77 vssa_79 vssa_81 vssa_82 vssa_85 vssa_88 vssa_91 vssa_94 vssa_95 vssc_11 vssc_3 vssc_4 vssc_7 vssc_8 vssd_15 vssd_22 vssd_32 vssd_44 vssd_54 vssd_64 vss_12 vss_72 tx aux2_n aux1_n aux1_p aux2_p aux2_n vdda33_100 vssa_99 vdda33_98 vssa_97 vdda33_96 90 89 86 87 6 5 37 75 92 93 83 84 73 71 36 35 24 21 20 19 18 17 34 31 30 29 28 27 26 25 59 58 47 46 45 42 41 40 57 56 55 52 51 50 49 48 pad vcc y nc a gnd 3 2 5 4 sn74lvc1g34 1 65 70 68 69 67 66 14 13 62 63 43 100 76 78 80 96 98 1 10 2 9 23 33 53 60 16 38 61 74 77 79 81 82 85 88 91 94 95 97 99 11 3 4 7 8 15 22 32 44 54 64 12 72 39 dvdd18 dvdd33 p2d15 dpwr33 dpwr33 dpwr33 tp11 red + c12 0.1f c30 1nf c13 0.1f r59 22 ? r26 22? r26 22 ? c5 4.7f c58 1nf volt cvdd18 avdd33 clk_n clk_p + c55 0.1f c57 0.1f c56 1nf c31 1nf s15 1 2 c14 0.1f c6 4.7f c40 0.1f volt + c36 1nf c35 1nf c39 0.1f c27 1nf c11 0.1f c3 4.7f c33 1nf jp4 d1n d1p jp8 volt + c37 0.1f c24 1nf c9 0.1f c1 4.7f + c62 0.1f c34 1nf volt + c38 0.1f c25 1nf c10 0.1f c2 4.7f c59 1nf c61 1nf c60 0.1f c18 1nf c8 10f 6.3v volt volt + c15 1nf c7 4.7f c32 0.1f + c78 4.7f s2 s7 dataclk 1 2 1 2 s16 1 2 u10 74lcx112 74lcx112 k clr pre j q_ q 5 2 15 4 3 1 6 5 3 1 4 2 r63 10 ? r7 0 ? r11 50? r10 50 ? r8 0 ? r32 25 ? r58 22 ? 7 u10 k clr pre j q_ q 9 12 14 10 11 13 c84 0.1f r56 10? r64 1k? cr1 val jp13 jp3 d2p d2n jp2 jp16 jp17 r64 1k? dpwr33 dgnd;5 cr2 val 3 4 1 2 sw1 4 6 p 3 s adtl1-12 t4b 1 3 1 1 4 2 2 tc1-1t t4a s6 6 4 6 p 3 s adtl1-12 t3b 1 3 1 4 2 tc1-1t t3a 6 1 3 s 6 p adtl1-12 t1b 4 tc1-1t t1a 1 3 s 6 p adtl1-12 t2b 4 1 3 6 2 1 3 2 tc1-1t t2a 4 6 4 1 2 s5 r6 0 ? r11 50 ? r9 50? r5 0 ? jp14 jp15 05361-102 figure 105. evaluation board, rev. d, circuitry local to devices
ad9776/ad9778/ad9779 rev. a | page 51 of 56 g2 enbl vps1 g1a g1b loip vps2 g4a g4b qbbp vout g3 ibbp ibbn qbbn loin ad8349 9 8 7 3 4 6 12 13 14 16 11 10 1 21 5 5 u9 vddm dgnd2 vddm r14 1k? jp1 j4 c47 100pf c72 0.1f c73 0.1f c41 10f 10v 2 2 1 dgnd2 2 dgnd2 2 dgnd2 2 dgnd2 2 dgnd2 dgnd2 modulated output 2 j5 jp9 2 1 dgnd2 local osc output c74 100pf c54 0.1f c79 17.2pf c65 17.2pf c75 100pf c51 0.1f + jp13 r60 40? r2 150? r3 150? r25 150? r61 40? 1 3 p 5 2 s etc1-1-13 t4 4 6 4 p 1 s adtl1-12 t3 3 jp10 r24 20 ? r62 147.5 ? c82 2.1pf l11 55nh c43 17.2pf c44 17.2pf c83 2.1pf l10 55nh r27 300 ? d2n d2p aux2_p aux2_n r23 20 ? c53 0.1f c52 17.2pf c50 17.2pf jp13 r20 40? r4 150? r12 150? r17 150? r21 40? 6 4 p 1 s adtl1-12 t5 3 r15 20 ? r22 147.5 ? c81 2.1pf l11 55nh c63 17.2pf c64 17.2pf c80 2.1pf l10 55nh r19 300 ? d1n d1p aux1_p aux1_n r16 20 ? 05361-103 figure 106. evaluation board, rev. d, ad8349 quadrature modulator 4 5 s 3 2 r13 val r30 1k : r31 300 : r28 25 : r29 25 : p etc1-1-13 t2 j1 clkin c19 0.1 p f c16 dnb cvdd18 clk_p clk_n c17 0.1 p f c23 0.1 p f 1 05361-104 figure 107. evaluation board, rev. d, dac clock interface
ad9776/ad9778/ad9779 rev. a | page 52 of 56 a1 p4 pkg_type = molex110 val a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 c1 p4 pkg_type = molex110 val c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c15 c16 c17 c18 c19 c20 c21 c22 c23 c24 c25 csb sd1 p2d0 p2d2 p2d4 p2d6 p2d8 p2d10 p2d12 p2d14 p1d0 p1d2 p1d4 p1d6 p1d8 p1d10 p1d12 p1d14 dgnd blk e1 p4 pkg_type = molex110 val e2 e3 e4 e5 e6 e7 e8 e9 e10 e11 e15 e16 e17 e18 e19 e20 e21 e22 e23 e24 e25 sclk sd0 p2d1 p2d3 p2d5 p2d7 p2d9 p2d11 p2d13 p2d15 p1d1 p1d3 p1d5 p1d7 p1d9 p1d11 p1d13 p1d15 b1 p4 pkg_type = molex110 val b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25 d1 p4 pkg_type = molex110 val d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 dgnd1 blk 05361-105 figure 108. evaluation board, rev. d, digital input buffers val cnterm_2p 1 2 j 2 5v 1 2 3 4 u2 adp3339-1-8 cvdd18_in jp19 c85 1 f c86 1 f 1 p2 2 1 2 3 4 u8 adp3339-3-3 dpwr33_in jp23 c97 1 f c96 1 f 1 2 3 4 u7 adp3339-3-3 avdd33_in jp22 c94 1 f c93 1 f 1 2 3 4 u4 adp3339-3-3 dvdd33_in jp21 c91 1 f c92 1 f 1 2 3 4 u3 adp3339-1-8 dvdd18_in jp20 c88 1 f c89 1 f 05361-106 figure 109. evaluation board, on-board voltage regulators
ad9776/ad9778/ad9779 rev. a | page 53 of 56 05361-107 figure 110. evaluation board, rev. d, top silk screen 05361-108 figure 111. evaluation board, rev. d, top layer
ad9776/ad9778/ad9779 rev. a | page 54 of 56 05361-109 figure 112. evaluation board, rev. d, layer 2 05361-110 figure 113. evaluation board, rev. d, layer 3
ad9776/ad9778/ad9779 rev. a | page 55 of 56 05361-111 figure 114. evaluation board, rev. d, bottom layer 05361-112 figure 115. evaluation board, rev. d, bottom silkscreen
ad9776/ad9778/ad9779 rev. a | page 56 of 56 outline dimensions notes 1. center figures are typical unless otherwise noted. 2 . the package has a conductive heat slug to help dissipate heat and ensure reliable operation o f the device over the full industrial temperature range. the slug is exposed on the bottom of the package and electrically connected to chip ground. it is recommended that no pcb signa l traces or vias be located under the package that could come in contact with the conductiv e slug. attaching the slug to a ground plane will reduce the junction temperature of the device which may be beneficial in high temperature environments. compliant to jedec standards ms-026-aed-hd 1 25 26 50 76 100 75 51 14.00 bsc sq 16.00 bsc sq 0.27 0.22 0.17 0.50 bsc 1.05 1.00 0.95 0.15 0.05 0.75 0.60 0.45 seating plane 1.20 max 1 25 26 50 76 100 75 51 6.50 nom 7 3.5 0 coplanarity 0.08 0.20 0.09 top view (pins down) bottom view (pins up) conductive heat sink pin 1 figure 116. 100-lead thin quad flat package, exposed pad [tqfp_ep] (sv-100-1) dimensions shown in millimeters ordering guide model temperature range package description package option ad9776bsvz 1 ?40 c to +85 c 100-lead tqfp_ep sv-100-1 ad9776bsvzrl 1 ?40 c to +85 c 100-lead tqfp_ep sv-100-1 ad9778bsvz 1 ?40 c to +85 c 100-lead tqfp_ep sv-100-1 ad9778bsvzrl 1 ?40 c to +85 c 100-lead tqfp_ep sv-100-1 ad9779bsvz 1 ?40 c to +85 c 100-lead tqfp_ep sv-100-1 ad9779bsvzrl 1 ?40 c to +85 c 100-lead tqfp_ep sv-100-1 ad9776-eb evaluation board ad9778-eb evaluation board ad9779-ebz 1 evaluation board 1 z = rohs compliant part. ?2005C2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05361-0-3/07(a)

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